Design space exploration and implementation of a high performance and low area Coarse Grained Reconfigurable Processor. - Dongkwan Suh; Kiseok Kwon; Sukjin Kim; Soojung Ryu; Jeongwook Kim (FPT, 2012)

Nop compression scheme for high speed DSPs based on VLIW architecture. - Taisong Jin; Minwook Ahn; Donghoon Yoo; Dongkwan Suh; Yoonseo Choi; Do Hyung Kim 002; Shihwa Lee (ICCE, 2014)

Improving Energy Efficiency of Coarse-Grain Reconfigurable Arrays Through Modulo Schedule Compression/Decompression. - Hochan Lee; Mansureh S. Moghaddam; Dongkwan Suh; Bernhard Egger 002 (ACM Trans. Archit. Code Optim., 2018)