Accurate geometric correction of ATSR images. - Dongseok Shin; John K. Pollard; Jan-Peter Muller (IEEE Trans. Geosci. Remote. Sens., 1997)

Estimation of the error performance objectives for satellite communication systems. - Sooyoung Kim Shin; Sungmoon Yeo; Dongseok Shin; Sang Seob Song (Int. J. Satell. Commun. Netw., 2008)

A 0.6-V, 30-GHz six-phase VCO with superharmonic coupling in 32-nm SOI CMOS technology. - Dongseok Shin; Sanjay Raman; Kwang-Jin Koh (CICC, 2015)

On-Orbit Camera Misalignment Estimation Framework and Its Application to Earth Observation Satellite. - Seungwoo Lee; Dongseok Shin (Remote. Sens., 2015)

2.8 A mixed-mode injection frequency-locked loop for self-calibration of injection locking range and phase noise in 0.13µm CMOS. - Dongseok Shin; Sanjay Raman; Kwang-Jin Koh (ISSCC, 2016)

Instability of oxide thin film transistor under electrical-mechanical hybrid stress for foldable display. - Dongseok Shin; Min Soo Bae; Ilgu Yun (Microelectron. Reliab., 2016)

Structure variation effects on device reliability of single photon avalanche diodes. - Dongseok Shin; Byungchoul Park; Youngcheol Chae; Ilgu Yun (Microelectron. Reliab., 2017)

A low-power 3.25GS/s 4th-order programmable analog FIR filter using split-CDAC coefficient multipliers for wideband analog signal processing. - Shinwoong Park; Dongseok Shin; Kwang-Jin Koh; Sanjay Raman (ISSCC, 2018)

A Fast Triple-Interferer Sensor (Detector and Digital Encoder) with In-Situ Reference Frequency Acquisition at 2.7-to-3.7GHz in 0.13μM CMOS. - Dongseok Shin; Kwang-Jin Koh (VLSI Circuits, 2018)

An Injection Frequency-Locked Loop - Autonomous Injection Frequency Tracking Loop With Phase Noise Self-Calibration for Power-Efficient mm-Wave Signal Sources. - Dongseok Shin; Kwang-Jin Koh (IEEE J. Solid State Circuits, 2018)

24-GHz Injection-Locked Frequency Tripler With Third-Harmonic Quadrature Phase Generator. - Dongseok Shin; Kwang-Jin Koh (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS. - Jihwan Kim; Sandipan Kundu; Ajay Balankutty; Matthew Beach; Bong Chan Kim; Stephen Kim; Yutao Liu; Savyassachi Keshava Murthy; Priya Wali; Kai Yu 016; Hyung Seok Kim; Chuanchang Liu; et al. (ISSCC, 2021)

11.5 A 23.9-to-29.4GHz Digital LC-PLL with a Coupled Frequency Doubler for Wireline Applications in 10nm FinFET. - Dongseok Shin; Hyung Seok Kim; Chuanchang Liu; Priya Wali; Savyasaachi Keshava Murthy; Yongping Fan (ISSCC, 2021)

A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET. - Jihwan Kim; Sandipan Kundu; Ajay Balankutty; Matthew Beach; Bong Chan Kim; Stephen T. Kim; Yutao Liu; Savyasaachi Keshava Murthy; Priya Wali; Kai Yu 016; Hyung Seok Kim; Chuanchang Liu; et al. (IEEE J. Solid State Circuits, 2022)

A Fractional-N Digital LC-PLL Using Coupled Frequency Doubler With Frequency-Tracking Loop for Wireline Applications. - Dongseok Shin; Hyung Seok Kim; Chuanchang Liu; Priya Wali; Savyasaachi Keshava Murthy; Yongping Fan (IEEE J. Solid State Circuits, 2022)

Minimization of Load Regulation in a Buck Converter Using Slope-Controlled Ripple Injection Method with Constant on- Time Control. - Chaiwon Kim; Hyeyoung Lee; Youngmin Cha; Dongseok Shin; Shihong Park (ICEIC, 2025)