A 0.011 mm2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI. - Aravind Tharayil Narayanan; Wei Deng 001; Dongsheng Yang 002; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (A-SSCC, 2014)

15.1 A 0.0066mm2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique. - Wei Deng 001; Dongsheng Yang 002; Tomohiro Ueno; Teerachot Siriburanon; Satoshi Kondo; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2014)

An HDL-synthesized gated-edge-injection PLL with a current output DAC. - Dongsheng Yang 002; Wei Deng 001; Tomohiro Ueno; Teerachot Siriburanon; Satoshi Kondo; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2015)

14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique. - Wei Deng 001; Dongsheng Yang 002; Aravind Tharayil Narayanan; Kengo Nakata; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2015)

A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI. - Dongsheng Yang 002; Wei Deng 001; Aravind Tharayil Narayanan; Rui Wu 001; Bangan Liu; Kenichi Okada 001; Akira Matsuzawa (IEICE Electron. Express, 2015)

A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique. - Wei Deng 001; Dongsheng Yang 002; Tomohiro Ueno; Teerachot Siriburanon; Satoshi Kondo; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2015)

An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection. - Dongsheng Yang 002; Wei Deng 001; Aravind Tharayil Narayanan; Kengo Nakata; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2016)

An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB. - Dongsheng Yang 002; Wei Deng 001; Bangan Liu; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2016)

A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI. - Dongsheng Yang 002; Tomohiro Ueno; Wei Deng 001; Yuki Terashima; Kengo Nakata; Aravind Tharayil Narayanan; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2016)

An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. - Dongsheng Yang 002; Wei Deng 001; Bangan Liu; Aravind Tharayil Narayanan; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2017)

A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI. - Aravind Tharayil Narayanan; Wei Deng 001; Dongsheng Yang 002; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2017)

A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique. - Bangan Liu; Huy Cu Ngo; Kengo Nakata; Wei Deng 001; Yuncheng Zhang; Junjun Qiu; Toru Yoshioka; Jun Emmei; Haosheng Zhang; Jian Pang; Aravind Tharayil Narayanan; Dongsheng Yang 002; et al. (CICC, 2018)

A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS. - Bangan Liu; Yun Wang 008; Jian Pang; Haosheng Zhang; Dongsheng Yang 002; Aravind Tharayil Narayanan; Dae Young Lee; Sung Tae Choi; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2018)