Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design. - Mingoo Seok; Dongsuk Jeon; Chaitali Chakrabarti; David T. Blaauw; Dennis Sylvester (DAC, 2011)

Energy-optimized high performance FFT processor. - Dongsuk Jeon; Mingoo Seok; Chaitali Chakrabarti; David T. Blaauw; Dennis Sylvester (ICASSP, 2011)

A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining. - Mingoo Seok; Dongsuk Jeon; Chaitali Chakrabarti; David T. Blaauw; Dennis Sylvester (ISSCC, 2011)

Extending energy-saving voltage scaling in ultra low voltage integrated circuit designs. - Mingoo Seok; Dongsuk Jeon; Chaitali Chakrabarti; David T. Blaauw; Dennis Sylvester (ICICDT, 2012)

A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS. - Dongsuk Jeon; Mingoo Seok; Chaitali Chakrabarti; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2012)

Design Methodology for Voltage-Overscaled Ultra-Low-Power Systems. - Dongsuk Jeon; Mingoo Seok; Zhengya Zhang; David T. Blaauw; Dennis Sylvester (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A low-power VGA full-frame feature extraction processor. - Dongsuk Jeon; Yejoong Kim; Inhee Lee 001; Zhengya Zhang; David T. Blaauw; Dennis Sylvester (ICASSP, 2013)

A 470mV 2.7mW feature extraction-accelerator for micro-autonomous vehicle navigation in 28nm CMOS. - Dongsuk Jeon; Yejoong Kim; Inhee Lee 001; Zhengya Zhang; David T. Blaauw; Dennis Sylvester (ISSCC, 2013)

Circuit techniques for miniaturized biomedical sensors. - Inhee Lee 001; Yejoong Kim; Suyoung Bang; Gyouho Kim; Hyunsoo Ha; Yen-Po Chen; Dongsuk Jeon; Seokhyun Jeong; Wanyeong Jung; Mohammad Hassan Ghaed; Zhiyoong Foo; Yoonmyung Lee; et al. (CICC, 2014)

24.3 An implantable 64nW ECG-monitoring mixed-signal SoC for arrhythmia diagnosis. - Dongsuk Jeon; Yen-Po Chen; Yoonmyung Lee; Yejoong Kim; Zhiyoong Foo; Grant H. Kruger; Hakan Oral; Omer Berenfeld; Zhengya Zhang; David T. Blaauw; Dennis Sylvester (ISSCC, 2014)

An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS. - Dongsuk Jeon; Michael B. Henry; Yejoong Kim; Inhee Lee 001; Zhengya Zhang; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2014)

A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory. - Dongsuk Jeon; Qing Dong 001; Yejoong Kim; Xiaolong Wang; Shuai Chen; Hao Yu 001; David T. Blaauw; Dennis Sylvester (VLSIC, 2015)

A 120nW 8b sub-ranging SAR ADC with signal-dependent charge recycling for biomedical applications. - Seokhyeon Jeong; Wanyeong Jung; Dongsuk Jeon; Omer Berenfeld; Hakan Oral; Grant H. Kruger; David T. Blaauw; Dennis Sylvester (VLSIC, 2015)

An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring. - Yen-Po Chen; Dongsuk Jeon; Yoonmyung Lee; Yejoong Kim; Zhiyoong Foo; Inhee Lee 001; Nicholas B. Langhals; Grant H. Kruger; Hakan Oral; Omer Berenfeld; Zhengya Zhang; David T. Blaauw; et al. (IEEE J. Solid State Circuits, 2015)

Live demonstration: A 128-channel spike sorting processor featuring 0.175 μW and 0.0033 mm2 per Channel in 65-nm CMOS. - Seyed Mohammad Ali Zeinolabedin; Anh-Tuan Do; Dongsuk Jeon; Dennis Sylvester; Tony Tae-Hyoung Kim (APCCAS, 2016)

Design techniques for ultra-efficient computing. - Dongsuk Jeon (ISOCC, 2016)

24.1 A 0.6V 8mW 3D vision processor for a navigation device for the visually impaired. - Dongsuk Jeon; Nathan Ickes; Priyanka Raina; Hsueh-Cheng Wang; Daniela Rus; Anantha P. Chandrakasan (ISSCC, 2016)

A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm2 per channel in 65-nm CMOS. - Seyed Mohammad Ali Zeinolabedin; Anh-Tuan Do; Dongsuk Jeon; Dennis Sylvester; Tony Tae-Hyoung Kim (VLSI Circuits, 2016)

8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment. - Tae-Kwang Jang; Seokhyeon Jeong; Dongsuk Jeon; Kyojin David Choo; Dennis Sylvester; David T. Blaauw (ISSCC, 2017)

A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS. - Dongsuk Jeon; Qing Dong 001; Yejoong Kim; Xiaolong Wang; Shuai Chen; Hao Yu 001; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2017)

A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector. - Tae-Kwang Jang; Seokhyeon Jeong; Dongsuk Jeon; Kyojin David Choo; Dennis Sylvester; David T. Blaauw (IEEE J. Solid State Circuits, 2018)

A 65nm 236.5nJ/Classification Neuromorphic Processor with 7.5% Energy Overhead On-Chip Learning Using Direct Spike-Only Feedback. - Jeongwoo Park; Juyun Lee; Dongsuk Jeon (ISSCC, 2019)

Microarchitecture-Aware Code Generation for Deep Learning on Single-ISA Heterogeneous Multi-Core Mobile Processors. - Junmo Park; Yongin Kwon; Yongjun Park 001; Dongsuk Jeon (IEEE Access, 2019)

Improving GPU Multitasking Efficiency Using Dynamic Resource Sharing. - Jiho Kim; Jehee Cha; Jason Jong Kyu Park; Dongsuk Jeon; Yongjun Park 001 (IEEE Comput. Archit. Lett., 2019)

Power-up control techniques for reliable SRAM PUF. - Juyun Lee; Dong-Woo Jee; Dongsuk Jeon (IEICE Electron. Express, 2019)

An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175µW/Channel in 65-nm CMOS. - Anh-Tuan Do; Seyed Mohammad Ali Zeinolabedin; Dongsuk Jeon; Dennis Sylvester; Tony Tae-Hyoung Kim (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Enhancing Reliability of Analog Neural Network Processors. - Suhong Moon; Kwanghyun Shin; Dongsuk Jeon (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A Modified Serial Commutator Architecture for Real-Valued Fast Fourier Transform. - Sungjin Park; Dongsuk Jeon (SiPS, 2020)

A Fast Finite Field Multiplier for SIKE. - Yeonsoo Jeon; Dongsuk Jeon (CoRR, 2020)

A 65-nm Neuromorphic Image Classification Processor With Energy-Efficient Training Through Direct Spike-Only Feedback. - Jeongwoo Park; Juyun Lee; Dongsuk Jeon (IEEE J. Solid State Circuits, 2020)

Real-Time Denoising and Dereverberation wtih Tiny Recurrent U-Net. - Hyeong-Seok Choi; Sungjin Park; Jie Hwan Lee; Hoon Heo; Dongsuk Jeon; Kyogu Lee (ICASSP, 2021)

Fast Automatic Circuit Optimization Using Deep Learning. - Jiwoo Hong; Sunghoon Kim; Jaeha Kim; Dongsuk Jeon (ISOCC, 2021)

Reducing Refresh Overhead with In-DRAM Error Correction Codes. - Hanbyeol Kwon; Kwangrae Kim; Dongsuk Jeon; Ki-Seok Chung (ISOCC, 2021)

A 40nm 4.81TFLOPS/W 8b Floating-Point Training Processor for Non-Sparse Neural Networks Using Shared Exponent Bias and 24-Way Fused Multiply-Add Tree. - Jeongwoo Park; Sunwoo Lee 005; Dongsuk Jeon (ISSCC, 2021)

Activation Sharing with Asymmetric Paths Solves Weight Transport Problem without Bidirectional Connection. - Sunghyeon Woo; Jeongwoo Park; Jiwoo Hong; Dongsuk Jeon (NeurIPS, 2021)

Real-time Denoising and Dereverberation with Tiny Recurrent U-Net. - Hyeong-Seok Choi; Sungjin Park; Jie Hwan Lee; Hoon Heo; Dongsuk Jeon; Kyogu Lee (CoRR, 2021)

A Multi-Channel Spike Sorting Processor With Accurate Clustering Algorithm Using Convolutional Autoencoder. - Changyu Seong; Wonjae Lee; Dongsuk Jeon (IEEE Trans. Biomed. Circuits Syst., 2021)

A 65nm 0.6-1.2V Low-Dropout Regulator Using Voltage-Difference-to-Time Converter With Direct Output Feedback. - Kwanghyun Shin; Dong-Woo Jee; Dongsuk Jeon (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Dynamic Block-Wise Local Learning Algorithm for Efficient Neural Network Training. - Gwangho Lee; Sunwoo Lee 005; Dongsuk Jeon (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A low power neural network training processor with 8-bit floating point with a shared exponent bias and fused multiply add trees. - Jeongwoo Park; Sunwoo Lee 005; Dongsuk Jeon (AICAS, 2022)

A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training. - Sangsu Jeong; Jeongwoo Park; Dongsuk Jeon (ESSCIRC, 2022)

Toward Efficient Low-Precision Training: Data Format Optimization and Hysteresis Quantization. - Sunwoo Lee 005; Jeongwoo Park; Dongsuk Jeon (ICLR, 2022)

A Neural Network Training Processor With 8-Bit Shared Exponent Bias Floating Point and Multiple-Way Fused Multiply-Add Trees. - Jeongwoo Park; Sunwoo Lee 005; Dongsuk Jeon (IEEE J. Solid State Circuits, 2022)

An Automatic Circuit Design Framework for Level Shifter Circuits. - Jiwoo Hong; Sunghoon Kim; Dongsuk Jeon (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

An In-Memory Computing SRAM Macro for Memory-Augmented Neural Network. - Sunghoon Kim; Wonjae Lee; Sundo Kim; Sungjin Park; Dongsuk Jeon (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 270-mA Self-Calibrating-Clocked Output-Capacitor-Free LDO With 0.15-1.15V Output Range and 0.183-fs FoM. - Youngmin Park; Dongsuk Jeon (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A 4.27TFLOPS/W FP4/FP8 Hybrid-Precision Neural Network Training Processor Using Shift-Add MAC and Reconfigurable PE Array. - Sunwoo Lee 005; Jeongwoo Park; Dongsuk Jeon (ESSCIRC, 2023)

Learning with Auxiliary Activation for Memory-Efficient Training. - Sunghyeon Woo; Dongsuk Jeon (ICLR, 2023)

A0.81 mm2 740μW Real-Time Speech Enhancement Processor Using Multiplier-Less PE Arrays for Hearing Aids in 28nm CMOS. - Sungjin Park; Sunwoo Lee 005; Jeongwoo Park; Hyeong-Seok Choi; Dongsuk Jeon (ISSCC, 2023)

Curriculum Reinforcement Learning From Avoiding Collisions to Navigating Among Movable Obstacles in Diverse Environments. - Hsueh-Cheng Wang; Siao-Cing Huang; Po-Jui Huang; Kuo-Lun Wang; Yi-Chen Teng; Yu-Ting Ko; Dongsuk Jeon; I-Chen Wu (IEEE Robotics Autom. Lett., 2023)

A Real-Time Object Detection Processor With xnor-Based Variable-Precision Computing Unit. - Wonjae Lee; Kukbyung Kim; Woohyun Ahn; Jinho Kim; Dongsuk Jeon (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 65 nm 12.92-nJ/Inference Mixed-Signal Neuromorphic Processor for Image Classification. - Yejun Ko; Sunghoon Kim; Kwanghyun Shin; Youngmin Park; Sundo Kim; Dongsuk Jeon (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 28nm 157TOPS/W 446.9Kb/mm2 Compute-In-Memory SRAM Macro with Analog-Digital Hybrid Computing for Deep Neural Network Inference. - Sangsu Jeong; Juyoung Oh; Dongsuk Jeon (CICC, 2024)

A 28nm All-Digital Droop Detection and Mitigation Circuit Using a Shared Dual-Mode Delay Line with 14.8% VminReduction and 42.9% Throughput Gain. - Minyoung Kang; Sunghoon Kim; Youngmin Park; Sangsu Jeong; Dongsuk Jeon (CICC, 2024)

ALAM: Averaged Low-Precision Activation for Memory-Efficient Training of Transformer Models. - Sunghyeon Woo; Sunwoo Lee 005; Dongsuk Jeon (ICLR, 2024)

DropBP: Accelerating Fine-Tuning of Large Language Models by Dropping Backward Propagation. - Sunghyeon Woo; Baeseong Park; Byeongwook Kim; Minjung Jo; Se Jung Kwon; Dongsuk Jeon; Dongsoo Lee (NeurIPS, 2024)

A 5.6µW 10-Keyword End-to-End Keyword Spotting System Using Passive-Averaging SAR ADC and Sign-Exponent-Only Layer Fusion with 92.7% Accuracy. - Sungjin Park; Kwanghyun Shin; Dongkwon Lee; Minyoung Kang; Sunwoo Lee 005; Youngmin Park; Mingoo Seok; Dongsuk Jeon (VLSI Technology and Circuits, 2024)

DropBP: Accelerating Fine-Tuning of Large Language Models by Dropping Backward Propagation. - Sunghyeon Woo; Baeseong Park; Byeongwook Kim; Minjung Jo; Sejung Kwon; Dongsuk Jeon; Dongsoo Lee (CoRR, 2024)

WITCH: WeIghTed Coding Scheme for Crosstalk Reduction in High Bandwidth Memory. - Seoyoon Jang; Sangouk Jeon; Kwanghyun Shin; Dongkwon Lee; Hankyu Chi; Wookjin Shin; Changhyun Pyo; Jaeha Kim; Dongsuk Jeon (ASP-DAC, 2025)

Efficient Key Switching Accelerator for Fully Homomorphic Encryption. - Seoyoon Jang; Sungjin Park; Dongsuk Jeon (ASP-DAC, 2025)

An 83.16-TOPS/W Voltage-Scalable Time-Domain CNN Accelerator with Full-Swing Delay Cell and Gray-Code TDC in 28-nm CMOS. - Sangsu Jeong; Huiwon Yun; Dongkwon Lee; Sunwoo Lee 005; Minyoung Kang; Dongsuk Jeon (CICC, 2025)

A 28-nm Real-Time Reinforcement Learning Processor for Mapless Autonomous Navigation with Unified Actor-Critic Network and Inference-on-Request Scheduling. - Juyoung Oh; Jie-Xin Liu; Yi-Chen Teng; Hsueh-Cheng Wang; Dongsuk Jeon (CICC, 2025)

PaCA: Partial Connection Adaptation for Efficient Fine-Tuning. - Sunghyeon Woo; Sol Namkung; Sunwoo Lee 005; Inho Jeong; Beomseok Kim; Dongsuk Jeon (ICLR, 2025)

Input-adaptive Mixed-Precision Framework for Efficient Object Detection. - Isaac Jeong; Ji-Ye Jeon; Kihwan Kim; Dongsuk Jeon; Hyuk-Jae Lee (ISCAS, 2025)

LogSimViT: Logarithmic Similar Pattern Skipping for Hardware Acceleration of ViT. - Isaac Jeong; Kihwan Kim; Seongho Jeong; Dongsuk Jeon; Hyuk-Jae Lee (ISCAS, 2025)

Cost-Effective Reconfigurable MCM with Common-Value Elimination and Alignment. - Kihwan Kim; Xuan Truong Nguyen; Dongsuk Jeon; Hyuk-Jae Lee (ISCAS, 2025)

A 28nm 18.1µJ /Acquisition End-to-End GPS Acquisition Accelerator with Energy-Accuracy-Driven Mixed-Radix IFFT and ROM-Assisted Computing. - Sangsu Jeong; Sungjin Park; Mingoo Seok; Dongsuk Jeon (ISSCC, 2025)

A Light Detector Capacitance Compensation Technique Achieving Boosted Active Quenching for Single-Photon Avalanche Diodes. - Sundo Kim; Jinseok Oh; Dongsuk Jeon; Inyong Kwon (IEEE Trans. Instrum. Meas., 2025)

A Dual Active Quenching Circuit With Temperature Compensation Technique for Breakdown Voltage Shift of Single-Photon Avalanche Diodes. - Sundo Kim; Jinseok Oh; Dongsuk Jeon; Inyong Kwon (IEEE Trans. Instrum. Meas., 2025)

A Real-Time Speech Enhancement Processor for Hearing Aids in 28-nm CMOS. - Sungjin Park; Sunwoo Lee 005; Jeongwoo Park; Hyeong-Seok Choi; Kyogu Lee; Dongsuk Jeon (IEEE J. Solid State Circuits, 2025)