A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques. - Kihwan Seong; Donguk Park; Gyeom-Je Bae; Hyunwoo Lee; Youngseob Suh; Wooseuk Oh; Hyemun Lee; Juyoung Kim; Takgun Lee; Geonhoo Mo; Sukhyun Jung; Dongcheol Choi; et al. (ISSCC, 2023)

13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets. - Kihwan Seong; Wooseuk Oh; Hyunwoo Lee; Gyeom-Je Bae; Youngseob Suh; Hyemun Lee; Juyoung Kim; Eunsu Kim; Yeongeon Kang; Gunhu Mo; Youjin Lee; Mingyeong Kim; et al. (ISSCC, 2024)