A 2× load/store pipe for a low-power 1-GHz embedded processor. - Zongjian Chen; Daniel Murray; Steve Nishimoto; Mark H. Pearce; Max Oyker; Daniel Rodriguez; Robert Rogenmoser; Dongwook (Drew) Suh; Erik Supnet; Vincent von Kaenel; George Yiu (IEEE J. Solid State Circuits, 2003)