Ultra-Low-Latency Parallel SC Polar Decoding Architecture for 5G Wireless Communications. - Dongyun Kam; Youngjoo Lee (ISCAS, 2019)

Massive MIMO Systems With Low-Resolution ADCs: Baseband Energy Consumption vs. Symbol Detection Performance. - Seungsik Moon; In-Soo Kim; Dongyun Kam; Dong-Woo Jee; Junil Choi; Youngjoo Lee (IEEE Access, 2019)

Ultra-Low-Latency LDPC Decoding Architecture using Reweighted Offset Min-Sum Algorithm. - Sangbu Yun; Dongyun Kam; Jeongwon Choe; Byeong Yong Kong; Youngjoo Lee (ISCAS, 2020)

FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks. - Changhyeon Kim; Dongyoung Rim; Jeongwon Choe; Dongyun Kam; Giyoon Park; Seokki Kim; Youngjoo Lee (A-SSCC, 2021)

Low-Latency Polar Decoder Using Overlapped SCL Processing. - Dongyun Kam; Byeong Yong Kong; Youngjoo Lee (ICASSP, 2021)

Ultralow-Latency Successive Cancellation Polar Decoding Architecture Using Tree-Level Parallelism. - Dongyun Kam; Hoyoung Yoo; Youngjoo Lee (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. - Dongyun Kam; Jung Gyu Min; Jongho Yoon 001; Sunmean Kim; Seokhyeong Kang; Youngjoo Lee (DATE, 2022)

A 1.1μs 1.56Gb/s/mm2 Cost-Efficient Large-List SCL Polar Decoder Using Fully-Reusable LLR Buffers in 28nm CMOS Technology. - Dongyun Kam; Byeong Yong Kong; Youngjoo Lee (VLSI Technology and Circuits, 2022)

Simplified Ordered Statistic Decoding for Short-Length Linear Block Codes. - Changhyeon Kim; Dongyun Kam; Seokki Kim; Giyoon Park; Youngjoo Lee (IEEE Commun. Lett., 2022)

Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm. - Seungwoo Hong; Dongyun Kam; Sangbu Yun; Jeongwon Choe; Namyoon Lee; Youngjoo Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

GROW: A Row-Stationary Sparse-Dense GEMM Accelerator for Memory-Efficient Graph Convolutional Neural Networks. - Ranggi Hwang; Minhoo Kang; Jiwon Lee; Dongyun Kam; Youngjoo Lee; Minsoo Rhu (HPCA, 2023)

Energy-Efficient RISC-V-Based Vector Processor for Cache-Aware Structurally-Pruned Transformers. - Jung Gyu Min; Dongyun Kam; Younghoon Byun; Gunho Park; Youngjoo Lee (ISLPED, 2023)

Low-Latency SCL Polar Decoder Architecture Using Overlapped Pruning Operations. - Dongyun Kam; Byeong Yong Kong; Youngjoo Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Constrained Sorter Design using Zero-One Principle. - Sangil Han; Jaehee Kim; Dongyun Kam; Byeong Yong Kong; Mijung Kim; Young-Seok Kim; Youngjoo Lee (ISCAS, 2024)

2.8 A 21.9ns 15.7 Gbps/mm² (128,15) BOSS FEC Decoder for 5G/6G URLLC Applications. - Dongyun Kam; Sangbu Yun; Jeongwon Choe; Zhengya Zhang; Namyoon Lee; Youngjoo Lee (ISSCC, 2024)

Hard-Decision SCL Polar Decoder With Weighted Pruning Operation for Storage Applications. - Dain Park; Dongyun Kam; Sangbu Yun; Jeongwon Choe; Youngjoo Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Design Framework for Cost-Efficient Sorters With Arbitrary Input/Output Constraints. - Jaehee Kim; Sangil Han; Dongyun Kam; Byeong Yong Kong; Youngjoo Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Panacea: Novel DNN Accelerator using Accuracy-Preserving Asymmetric Quantization and Energy-Saving Bit-Slice Sparsity. - Dongyun Kam; Myeongji Yun; Sunwoo Yoo; Seungwoo Hong; Zhengya Zhang; Youngjoo Lee (HPCA, 2025)