A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network. - Dongzhu Li; Yao-Chung Hsu; Rei Sumikawa; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (ISCAS, 2023)

Efficient FPGA Resource Utilization in Wired-Logic Processors Using Coarse and Fine Segmentation of LUTs for Non-Linear Functions. - Dongzhu Li; Tianqi Zhao; Kenji Kobayashi; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (ISCAS, 2024)

A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA. - Dongzhu Li; Zhijie Zhan; Rei Sumikawa; Mototsugu Hamada; Atsutake Kosuge; Tadahiro Kuroda (IEICE Trans. Electron., 2024)

A Coarse- and Fine-Grained LUT Segmentation Method Enabling Single FPGA Implementation of Wired-Logic DNN Processor. - Yuxuan Pan; Dongzhu Li; Mototsugu Hamada; Atsutake Kosuge (ASP-DAC, 2025)

13.6 A Via-Programmable DNN-Processor Fabrication Toward 1/40th Mask Cost. - Jaewon Shin; Rei Sumikawa; Dongzhu Li; Mototsugu Hamada; Atsutake Kosuge (ISSCC, 2025)

Analysis and Design of Coarse and Fine Segmented LUT Implementation for FPGA-Based Resource Efficient Wired-Logic DNN Processors. - Yuxuan Pan; Dongzhu Li; Mototsugu Hamada; Atsutake Kosuge (IEICE Trans. Electron., 2025)