A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure. - Ki-Tae Park; Doo-Gon Kim; Soonwook Hwang; Myounggon Kang; Hoosung Cho; Youngwook Jeong; Yong-Il Seo; Jae-hoon Jang; Hansoo Kim; Soon-Moon Jung; Yeong-Taek Lee; Changhyun Kim; et al. (ISSCC, 2008)

A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories. - Ki-Tae Park; Myounggon Kang; Doogon Kim; Soonwook Hwang; Byung Yong Choi; Yeong-Taek Lee; Changhyun Kim; Kinam Kim (IEEE J. Solid State Circuits, 2008)

A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure. - Ki-Tae Park; Myounggon Kang; Soonwook Hwang; Doo-Gon Kim; Hoosung Cho; Youngwook Jeong; Yong-Il Seo; Jae-hoon Jang; Hansoo Kim; Yeong-Taek Lee; Soon-Moon Jung; Changhyun Kim (IEEE J. Solid State Circuits, 2009)

A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology. - Daeyeal Lee; Ik Joon Chang; Sangyong Yoon; Joonsuc Jang; Dong-Su Jang; Wook-Ghee Hahn; Jong-Yeol Park; Doo-Gon Kim; Chiweon Yoon; Bong-Soon Lim; ByungJun Min; Sung-Won Yun; et al. (ISSCC, 2012)

7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers. - Dongku Kang; Woopyo Jeong; Chulbum Kim; Doo-Hyun Kim; Yong-Sung Cho; Kyung-Tae Kang; Jinho Ryu; Kyung-Min Kang; Sungyeon Lee; Wandong Kim; Hanjun Lee; Jaedoeg Yu; et al. (ISSCC, 2016)

A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture. - Jae-Woo Park; Doogon Kim; Sunghwa Ok; Jaebeom Park; Taeheui Kwon; Hyunsoo Lee; Sungmook Lim; Sunyoung Jung; Hyeong-Jin Choi; Taikyu Kang; Gwan Park; Chul-Woo Yang; et al. (ISSCC, 2021)

Effects of Social Behaviors of Robots in Privacy-Sensitive Situations. - Daseul Yang; Yu-Jung Chae; Doogon Kim; Yoonseob Lim; Dong Hwan Kim; ChangHwan Kim 002; Sung-Kee Park; Changjoo Nam (Int. J. Soc. Robotics, 2022)