Producing a Bidirectional ATPG Compliant Verilog-HDL Memory Model of SRAM. - Dorian Ronga; Xhesila Xhafa; Eric Faehn; Patrick Girard 001; Thibault Vayssade; Arnaud Virazel (DTTIS, 2024)

Memory Dynamic Faults and Array-Level Faults Detector in Digital Test Environment. - Dorian Ronga; Eric Faehn; Patrick Girard 001; Arnaud Virazel (DFT, 2025)

A Digital SRAM Modeling for Cell-Aware Testing and Test Algorithms Evaluation. - Dorian Ronga; Xhesila Xhafa; Eric Faehn; Patrick Girard 001; T. Vayssade; Arnaud Virazel (IOLTS, 2025)

Pre-processing Functional And Physical Defect Equivalences To Accelerate Cell-Aware Model Generation. - Reza Khoshzaban; Gianmarco Mongelli; Dorian Ronga; Iacopo Guglielminetti; Michelangelo Grosso; Eric Faehn; Patrick Girard 001; Arnaud Virazel; Riccardo Cantoro (VTS, 2026)