Jitter model of direct digital synthesis clock generators. - Dorin Emil Calbaza; Yvon Savaria (ISCAS (1), 1999)

Direct digital frequency synthesis of low-jitter clocks. - Dorin Emil Calbaza; Yvon Savaria (IEEE J. Solid State Circuits, 2001)

A direct digital period synthesis circuit. - Dorin Emil Calbaza; Yvon Savaria (IEEE J. Solid State Circuits, 2002)

An ADPLL circuit using a DDPS for genlock applications. - Dorin Emil Calbaza; Ioan Cordos; Nigel Seth-Smith; Yvon Savaria (ISCAS (4), 2004)