Synthesising an asynchronous DMA controller with Balsa. - Andrew Bardsley; Doug A. Edwards (J. Syst. Archit., 2000)

A Burst-Mode Oriented Back-End for the Balsa Synthesis System. - Tiberiu Chelcea; Steven M. Nowick; Andrew Bardsley; Doug A. Edwards (DATE, 2002)

Balsa: An Asynchronous Hardware Synthesis Language. - Doug A. Edwards; Andrew Bardsley (Comput. J., 2002)

Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance. - Luis A. Plana; Sam Taylor; Doug A. Edwards (ICCD, 2005)

Synthesis of Asynchronous Circuits Using Early Data Validity. - Nitin Gupta; Doug A. Edwards (VLSI Design, 2005)

Performance-driven syntax-directed synthesis of asynchronous processors. - Luis A. Plana; Doug A. Edwards; Sam Taylor; Luis A. Tarazona; Andrew Bardsley (CASES, 2007)

Automatic Compilation of Data-Driven Circuits. - Sam Taylor; Doug A. Edwards; Luis A. Plana (ASYNC, 2008)

Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems. - José L. Núñez-Yáñez; Doug A. Edwards; Antonio Marcello Coppola (IET Comput. Digit. Tech., 2008)

Teak: A Token-Flow Implementation for the Balsa Language. - Andrew Bardsley; Luis A. Tarazona; Doug A. Edwards (ACSD, 2009)

Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks. - William B. Toms; Doug A. Edwards (ASYNC, 2009)

A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor. - Luis A. Tarazona; Doug A. Edwards; Luis A. Plana (DSD, 2009)

Building asynchronous routers with independent sub-channels. - Wei Song 002; Doug A. Edwards (SoC, 2009)

Dual-Sum Single-Carry Self-Timed Adder Designs. - P. Balasubramanian 001; Doug A. Edwards (ISVLSI, 2009)

Adaptive stochastic routing in fault-tolerant on-chip networks. - Wei Song 002; Doug A. Edwards; José Luis Núñez-Yáñez; Sohini Dasgupta (NOCS, 2009)

An Asynchronous Routing Algorithm for Clos Networks. - Wei Song 002; Doug A. Edwards (ACSD, 2010)

A low latency wormhole router for asynchronous on-chip networks. - Wei Song 002; Doug A. Edwards (ASP-DAC, 2010)

Computation reduction for statistical analysis of the effect of nano-CMOS variability on asynchronous circuits. - Zheng Xie; Doug A. Edwards (DDECS, 2010)

Description-Level Optimisation of Synthesisable Asynchronous Circuits. - Luis A. Tarazona; Doug A. Edwards; Andrew Bardsley; Luis A. Plana (DSD, 2010)

Asynchronous Data-Driven Circuit Synthesis. - Sam Taylor; Doug A. Edwards; Luis A. Plana; Luis A. Tarazona (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Asynchronous spatial division multiplexing router. - Wei Song 002; Doug A. Edwards (Microprocess. Microsystems, 2011)

Area efficient asynchronous SDM routers using 2-stage Clos switches. - Wei Song 002; Doug A. Edwards; Jim D. Garside; William J. Bainbridge (DATE, 2012)

Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits. - Zheng Xie; Doug A. Edwards (VLSI Design, 2013)

Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA. - Mahdi Jelodari Mamaghani; Jim D. Garside; William B. Toms; Doug A. Edwards (DSD, 2014)

Automatic data path extraction in large-scale register-transfer level designs. - Wei Song 002; Jim D. Garside; Doug A. Edwards (ISCAS, 2014)

De-elastisation: from asynchronous dataflows to synchronous circuits. - Mahdi Jelodari Mamaghani; Jim D. Garside; Doug A. Edwards (DATE, 2015)