New System-in-Package (SiP) Integration technologies. - Doug C. H. Yu (CICC, 2014)

Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology. - Chuei-Tang Wang; Jeng-Shien Hsieh; Victor C. Y. Chang; En-Hsiang Yeh; Feng-Wei Kuo; Hsu-Hsien Chen; Chih-Hua Chen; Huan-Neng Ron Chen; Ying-Ta Lu; Chewnpu Jou; Hao-Yi Tsai; C. S. Liu; et al. (3DIC, 2015)

Ultra High Power Cooling Solution for 3D-ICs. - C. J. Wu; S. T. Hsiao; J. Y. Wang; W. H. Lin; C. W. Chang; T. L. Shao; C. H. Tung; Doug C. H. Yu (VLSI Circuits, 2021)

SoIC_H Technology for Heterogenous System Integration. - Chuei-Tang Wang; Chia-Chai Lin; Chih-Hsin Lu; Wei-Ting Chen; Chung-Hao Tsai; Douglas C. H. Yu (VLSI Technology and Circuits, 2022)

An Integrated System Scaling Solution for Future High Performance Computing. - Chih-Hang Tung; Doug C. H. Yu (VLSI Technology and Circuits, 2023)

A 28-nm 141.4TOPS/W Scalable Reconfigurable Deep Learning SoC for Large-Scale Neural Networks. - I-Hsuan Liu; I-Ting Lin; Yueh-Feng Tsai; Jeng-Sheng Hsieh; Vincent Chen; Chuei-Tang Wang; Chia-Hsiang Yang; Douglas C. H. Yu (A-SSCC, 2024)