Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer. - Mitsuru Hiraki; Raminder Singh Bajwa; Hirotsugu Kojima; Douglas J. Gorny; Ken-ichi Nitta; Avadhani Shridhar; Katsuro Sasaki; Koichi Seki (ISLPED, 1996)

Instruction buffering to reduce power in processors for signal processing. - Raminder Singh Bajwa; Mitsuru Hiraki; Hirotsugu Kojima; Douglas J. Gorny; Ken-ichi Nitta; Avadhani Shridhar; Koichi Seki; Katsuro Sasaki (IEEE Trans. Very Large Scale Integr. Syst., 1997)