The estimation of subsample time delay of arrival in the discrete-time measurement of phase delay. - Douglas L. Maskell; Graham S. Woods (IEEE Trans. Instrum. Meas., 1999)

A frequency modulated envelope delay FSCW radar for multiple-target applications. - Douglas L. Maskell; Graham S. Woods (IEEE Trans. Instrum. Meas., 2000)

The discrete-time quadrature subsample estimation of delay. - Douglas L. Maskell; Graham S. Woods (IEEE Trans. Instrum. Meas., 2002)

Towards Run-Time Re-Configurable Techniques for Real-Time Embedded Applications. - Timothy F. Oliver; Douglas L. Maskell (Engineering of Reconfigurable Systems and Algorithms, 2003)

A hardware efficient implementation of an adaptive subsample delay estimator. - Douglas L. Maskell; Graham S. Woods; Andrew Kerans (ISCAS (3), 2004)

Software-Oriented System-Level Simulation for Design Space Exploration of Reconfigurable Architectures. - K. S. Tham; Douglas L. Maskell (Asia-Pacific Computer Systems Architecture Conference, 2005)

Biological Sequence Analysis with Hidden Markov Models on an FPGA. - Jacop Yanto; Timothy F. Oliver; Bertil Schmidt; Douglas L. Maskell (Asia-Pacific Computer Systems Architecture Conference, 2005)

Hyper customized processors for bio-sequence database scanning on FPGAs. - Timothy F. Oliver; Bertil Schmidt; Douglas L. Maskell (FPGA, 2005)

An FPGA Model for Developing Dynamic Circuit Computing. - Timothy F. Oliver; Douglas L. Maskell (FPT, 2005)

Multiple Sequence Alignment on an FPGA. - Timothy F. Oliver; Bertil Schmidt; Douglas L. Maskell; Darran Nathan; Ralf Clemens (ICPADS (2), 2005)

A reconfigurable architecture for scanning biosequence databases. - Timothy F. Oliver; Bertil Schmidt; Douglas L. Maskell; Achutavarrier Prasad Vinod (ISCAS (5), 2005)

Using reconfigurable hardware to accelerate multiple sequence alignment with ClustalW. - Timothy F. Oliver; Bertil Schmidt; Darran Nathan; Ralf Clemens; Douglas L. Maskell (Bioinform., 2005)

Adaptive subsample delay estimation using a modified quadrature phase detector. - Douglas L. Maskell; Graham S. Woods (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

Reconfigurable architectures for bio-sequence database scanning on FPGAs. - Timothy F. Oliver; Bertil Schmidt; Douglas L. Maskell (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

Automatic Identification of Custom Functions for Embedded Processors with MIMO Extensions. - Xiaoyong Chen; Douglas L. Maskell; Yang Sun (APCCAS, 2006)

Unified Signed-Digit Number Adder for RSA and ECC Public-key Cryptosystems. - Yi Wang 016; Douglas L. Maskell; Jussipekka Leiwo; Thambipillai Srikanthan (APCCAS, 2006)

M2E: A Multiple-Input, Multiple-Output Function Extension for RISC-Based Extensible Processors. - Xiaoyong Chen; Douglas L. Maskell (ARCS, 2006)

FCMAC-AARS: A Novel FNN Architecture for Stock Market Prediction and Trading. - Zaiyi Guo; Chai Quek; Douglas L. Maskell (IEEE Congress on Evolutionary Computation, 2006)

A Brain Inspired Fuzzy Neuro-predictor for Bank Failure Analysis. - Chee H. Lee; Chai Quek; Douglas L. Maskell (IEEE Congress on Evolutionary Computation, 2006)

Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System. - Douglas L. Maskell; Timothy F. Oliver (Dynamically Reconfigurable Architectures, 2006)

Execution Objects for Dynamically Reconfigurable FPGA Systems. - Timothy F. Oliver; Douglas L. Maskell (FPL, 2006)

Software-Oriented Approach to Hardware-Software Co-Simulation for FPGA-Based Risc Extensible Processor. - K. S. Tham; Douglas L. Maskell (FPL, 2006)

Accelerating the Viterbi Algorithm for Profile Hidden Markov Models Using Reconfigurable Hardware. - Timothy F. Oliver; Bertil Schmidt; Yanto Jakop; Douglas L. Maskell (International Conference on Computational Science (1), 2006)

The design of multiplierless FIR filters with a minimum adder step and reduced hardware complexity. - Douglas L. Maskell; Jussipekka Leiwo; Jagdish Chandra Patra (ISCAS, 2006)

High-speed Multiple Sequence Alignment on a reconfigurable platform. - Timothy F. Oliver; Bertil Schmidt; Douglas L. Maskell; Darran Nathan; Ralf Clemens (Int. J. Bioinform. Res. Appl., 2006)

A technique for expressing IT security objectives. - Jussipekka Leiwo; Lam-for Kwok; Douglas L. Maskell; Nenad Stankovic (Inf. Softw. Technol., 2006)

Adaptive subsample delay estimation using windowed correlation. - Douglas L. Maskell; Graham S. Woods (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Type-2 GA-TSK fuzzy neural network. - Alvin Cai; Chai Quek; Douglas L. Maskell (IEEE Congress on Evolutionary Computation, 2007)

An Embedded Systems graduate education for Singapore. - Ian McLoughlin 001; Douglas L. Maskell; Thambipillai Srikanthan; Wooi-Boon Goh (ICPADS, 2007)

C-Based Design Methodology for FPGA Implementation of ClustalW MSA. - Yan Lin Aung; Douglas L. Maskell; Timothy F. Oliver; Bertil Schmidt; William Bong (PRIB, 2007)

Prerouted FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System. - Timothy F. Oliver; Douglas L. Maskell (EURASIP J. Embed. Syst., 2007)

Design of efficient multiplierless FIR filters. - Douglas L. Maskell (IET Circuits Devices Syst., 2007)

Supporting multiple-input, multiple-output custom functions in configurable processors. - Xiaoyong Chen; Douglas L. Maskell (J. Syst. Archit., 2007)

Fast Identification of Custom Instructions for Extensible Processors. - Xiaoyong Chen; Douglas L. Maskell; Yang Sun (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Efficient multiplierless channel filters for multi-standard SDR. - Douglas L. Maskell; A. Prasad Vinod 001 (CIT, 2008)

Multiplierless multi-standard SDR channel filters. - Douglas L. Maskell; Achutavarrier Prasad Vinod; Graham S. Woods (MMSP, 2008)

A unified architecture for a public key cryptographic coprocessor. - Yi Wang 016; Douglas L. Maskell; Jussipekka Leiwo (J. Syst. Archit., 2008)

A Reconfigurable Bloom Filter Architecture for BLASTN. - Yupeng Chen; Bertil Schmidt; Douglas L. Maskell (ARCS, 2009)

MSA-CUDA: Multiple Sequence Alignment on Graphics Processing Units with CUDA. - Yongchao Liu; Bertil Schmidt; Douglas L. Maskell (ASAP, 2009)

Dynamic thermal-aware scheduling on chip multiprocessor for soft real-time system. - Jin Cui; Douglas L. Maskell (ACM Great Lakes Symposium on VLSI, 2009)

Workshop on Using Emerging Parallel Architectures for Computational Science. - Bertil Schmidt; Douglas L. Maskell (ICCS (1), 2009)

Parallel reconstruction of neighbor-joining trees for large multiple sequence alignments using CUDA. - Yongchao Liu; Bertil Schmidt; Douglas L. Maskell (IPDPS, 2009)

High Speed Biological Sequence Analysis With Hidden Markov Models on Reconfigurable Platforms. - Timothy F. Oliver; Bertil Schmidt; Yanto Jakop; Douglas L. Maskell (IEEE Trans. Inf. Technol. Biomed., 2009)

High level event driven thermal estimation for thermal aware task allocation and scheduling. - Jin Cui; Douglas L. Maskell (ASP-DAC, 2010)

A dependency graph based methodology for parallelizing HLL applications on FPGA (abstract only). - Sunita Chandrasekaran; Shilpa Shanbagh; Douglas L. Maskell (FPGA, 2010)

MSAProbs: multiple sequence alignment based on pair hidden Markov models and partition function posterior probabilities. - Yongchao Liu; Bertil Schmidt; Douglas L. Maskell (Bioinform., 2010)

An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth. - Achutavarrier Prasad Vinod; Edmund Ming-Kit Lai; Douglas L. Maskell; Pramod Kumar Meher (Integr., 2010)

CUDA-MEME: Accelerating motif discovery in biological sequences using CUDA-enabled graphics processing units. - Yongchao Liu; Bertil Schmidt; Weiguo Liu; Douglas L. Maskell (Pattern Recognit. Lett., 2010)

Second Workshop on using Emerging Parallel Architectures. - Bertil Schmidt; Douglas L. Maskell (ICCS, 2010)

EpiList II: Closing the Loop in the Development of Generic Cognitive Skills. - Ghee Ming Goh; Chai Quek; Douglas L. Maskell (IEEE Trans. Syst. Man Cybern. Part A, 2010)

An Ultrafast Scalable Many-Core Motif Discovery Algorithm for Multiple GPUs. - Yongchao Liu; Bertil Schmidt; Douglas L. Maskell (IPDPS Workshops, 2011)

Performance-Power Design Space Exploration in a Hybrid Computing Platform Suitable for Mobile Applications. - Ramkumar Jayaraman; Handi Kartadihardja; Douglas L. Maskell (ISED, 2011)

Estimation of external quantum efficiency for multi-junction solar cells under influence of charged particles using artificial neural networks. - Jagdish Chandra Patra; Lian Lian Jiang; Douglas L. Maskell (SMC, 2011)

CompleteMOTIFs: DNA motif discovery platform for transcription factor binding experiments. - Lakshmi Kuttippurathu; Michael Hsing; Yongchao Liu; Bertil Schmidt; Douglas L. Maskell; Kyungjoon Lee; Aibin He; William T. Pu; Sek Won Kong (Bioinform., 2011)

DecGPU: distributed error correction on massively parallel graphics processing units using CUDA and MPI. - Yongchao Liu; Bertil Schmidt; Douglas L. Maskell (BMC Bioinform., 2011)

Parallelized short read assembly of large genomes using de Bruijn graphs. - Yongchao Liu; Bertil Schmidt; Douglas L. Maskell (BMC Bioinform., 2011)

A Novel Fuzzy Associative Memory Architecture for Stock Market Prediction and Trading. - Chai Quek; Zaiyi Guo; Douglas L. Maskell (Int. J. Fuzzy Syst. Appl., 2011)

Third Workshop on using Emerging Parallel Architectures. - Bertil Schmidt; Douglas L. Maskell (ICCS, 2011)

A lean FPGA soft processor built using a DSP block. - Hui Yan Cheah; Suhaib A. Fahmy; Douglas L. Maskell; Chidamber Kulkarni (FPGA, 2012)

Accelerating short read mapping on an FPGA (abstract only). - Yupeng Chen; Bertil Schmidt; Douglas L. Maskell (FPGA, 2012)

An FPGA aligner for short read mapping. - Yupeng Chen; Bertil Schmidt; Douglas L. Maskell (FPL, 2012)

iDEA: A DSP block based FPGA soft processor. - Hui Yan Cheah; Suhaib A. Fahmy; Douglas L. Maskell (FPT, 2012)

A flann-based controller for maximum power point tracking in PV systems under rapidly changing conditions. - Lian Lian Jiang; Douglas L. Maskell; Jagdish Chandra Patra (ICASSP, 2012)

Chebyshev Functional Link Neural Network-based modeling and experimental verification for photovoltaic arrays. - Lian Lian Jiang; Douglas L. Maskell; Jagdish Chandra Patra (IJCNN, 2012)

CUSHAW: a CUDA compatible short read aligner to large genomes based on the Burrows-Wheeler transform. - Yongchao Liu; Bertil Schmidt; Douglas L. Maskell (Bioinform., 2012)

Fourth Workshop on using Emerging Parallel Architectures. - Bertil Schmidt; Douglas L. Maskell (ICCS, 2012)

A Fast High-Level Event-Driven Thermal Estimator for Dynamic Thermal Aware Scheduling. - Jin Cui; Douglas L. Maskell (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Microkernel hypervisor for a hybrid ARM-FPGA platform. - Khoa Dang Pham; Abhishek Kumar Jain; Jin Cui; Suhaib A. Fahmy; Douglas L. Maskell (ASAP, 2013)

Current-controlled resonant circuit based photovoltaic micro-inverter with half- wave cycloconverter. - D. R. Nayanasiri; D. Mahinda Vilathgamuwa; Douglas L. Maskell (IAS, 2013)

A simple and efficient hybrid maximum power point tracking method for PV systems under partially shaded condition. - Lian Lian Jiang; D. R. Nayanasiri; Douglas L. Maskell; D. Mahinda Vilathgamuwa (IECON, 2013)

High-frequency-link micro-inverter with front-end current-fed half-bridge boost converter and half-wave cycloconverter. - D. R. Nayanasiri; D. Mahinda Vilathgamuwa; Douglas L. Maskell (IECON, 2013)

Fuzzy interpolation and extrapolation using shift ratio and overall weight measurement based on areas of fuzzy sets. - Weigui Jair Zhou; Douglas Leslie Maskell; Chai Quek (UKCI, 2013)

A hybrid short read mapping accelerator. - Yupeng Chen; Bertil Schmidt; Douglas L. Maskell (BMC Bioinform., 2013)

C2FPGA - A dependency-timing graph design methodology. - Sunita Chandrasekaran; Shilpa Shanbagh; Ramkumar Jayaraman; Douglas L. Maskell; Hui Yan Cheah (J. Parallel Distributed Comput., 2013)

Reconfigurable Accelerator for the Word-Matching Stage of BLASTN. - Yupeng Chen; Bertil Schmidt; Douglas L. Maskell (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A uniform implementation scheme for evolutionary optimization algorithms and the experimental implementation of an ACO based MPPT for PV systems under partial shading. - Lian Lian Jiang; Douglas L. Maskell (CIASG, 2014)

Soft-switching single inductor current-fed push-pull converter for PV applications. - D. R. Nayanasiri; D. Mahinda Vilathgamuwa; Douglas L. Maskell; Gilbert Hock Beng Foo (IECON, 2014)

HFL micro inverter with front-end diode clamped multi-level inverter and half-wave cycloconverter. - Dulika R. Nayanasiri; D. Mahinda Vilathgamuwa; Douglas L. Maskell (ISIE, 2014)

The iDEA DSP Block-Based Soft Processor for FPGAs. - Hui Yan Cheah; Fredrik Brosser; Suhaib A. Fahmy; Douglas L. Maskell (ACM Trans. Reconfigurable Technol. Syst., 2014)

Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform. - Abhishek Kumar Jain; Khoa Dang Pham; Jin Cui; Suhaib A. Fahmy; Douglas L. Maskell (J. Signal Process. Syst., 2014)

Efficient Overlay Architecture Based on DSP Blocks. - Abhishek Kumar Jain; Suhaib A. Fahmy; Douglas L. Maskell (FCCM, 2015)

Automatic fault detection and diagnosis for photovoltaic systems using combined artificial neural network and analytical based methods. - Lian Lian Jiang; Douglas L. Maskell (IJCNN, 2015)

FIE-FCMAC: A novel fuzzy cerebellum model articulation controller (FCMAC) using fuzzy interpolation and extrapolation technique. - Weigui Jair Zhou; Douglas Leslie Maskell; Chai Quek (IJCNN, 2015)

A distributed minority and majority voting based redundancy scheme. - P. Balasubramanian 001; Douglas L. Maskell (Microelectron. Reliab., 2015)

Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq. - Abhishek Kumar Jain; Xiangwei Li; Suhaib A. Fahmy; Douglas L. Maskell (SIGARCH Comput. Archit. News, 2015)

An Improved Robust Field-Weakeaning Algorithm for Direct-Torque-Controlled Synchronous-Reluctance-Motor Drives. - Xinan Zhang 001; Gilbert Hock Beng Foo; D. Mahinda Vilathgamuwa; Douglas L. Maskell (IEEE Trans. Ind. Electron., 2015)

A racetrack memory based in-memory booth multiplier for cryptography application. - Tao Luo 014; Wei Zhang 012; Bingsheng He; Douglas L. Maskell (ASP-DAC, 2016)

Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs? - Abhishek Kumar Jain; Douglas L. Maskell; Suhaib A. Fahmy (DASC/PiCom/DataCom/CyberSciTech, 2016)

Throughput oriented FPGA overlays using DSP blocks. - Abhishek Kumar Jain; Douglas L. Maskell; Suhaib A. Fahmy (DATE, 2016)

DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect. - Abhishek Kumar Jain; Xiangwei Li; Pranjul Singhai; Douglas L. Maskell; Suhaib A. Fahmy (FCCM, 2016)

An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units. - Xiangwei Li; Abhishek Kumar Jain; Douglas L. Maskell; Suhaib A. Fahmy (CoRR, 2016)

A novel two-stage modular multiplier based on racetrack memory for asymmetric cryptography. - Tao Luo 014; Bingsheng He; Wei Zhang 012; Douglas L. Maskell (ICCAD, 2017)

Approximate quasi-delay-insensitive asynchronous adders: Design and analysis. - P. Balasubramanian 001; Cuong Dang; Douglas L. Maskell (MWSCAS, 2017)

Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays. - Abhishek Kumar Jain; Douglas L. Maskell; Suhaib A. Fahmy (CoRR, 2017)

Asynchronous Early Output Section-Carry Based Carry Lookahead Adder with Alias Carry Logic. - P. Balasubramanian 001; Cuong Dang; Douglas L. Maskell; K. Prasad (CoRR, 2017)

Approximate Ripple Carry and Carry Lookahead Adders - A Comparative Analysis. - P. Balasubramanian 001; Cuong Dang; Douglas L. Maskell; K. Prasad (CoRR, 2017)

A Hybrid Logic Block Architecture in FPGA for Holistic Efficiency. - Tao Luo 014; Hao Liang 003; Wei Zhang 012; Bingsheng He; Douglas L. Maskell (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A time-multiplexed FPGA overlay with linear interconnect. - Xiangwei Li; Abhishek Kumar Jain; Douglas L. Maskell; Suhaib A. Fahmy (DATE, 2018)

Indicating Asynchronous Multipliers. - P. Balasubramanian 001; Douglas L. Maskell; Nikos E. Mastorakis (EECS, 2018)

Asynchronous Early Output Block Carry Lookahead Adder with Improved Quality of Results. - P. Balasubramanian 001; Douglas L. Maskell; Nikos E. Mastorakis (MWSCAS, 2018)

Majority and Minority Voted Redundancy for Safety-Critical Applications. - P. Balasubramanian 001; Douglas L. Maskell; Nikos E. Mastorakis (MWSCAS, 2018)

A System Health Indicator for the Distributed Minority and Majority Voting Based Redundancy Scheme. - P. Balasubramanian 001; Douglas L. Maskell; Krishnamachar Prasad (TENCON, 2018)

Hardware Efficient Approximate Adder Design. - P. Balasubramanian 001; Douglas L. Maskell (TENCON, 2018)

A Self-Healing Redundancy Scheme for Mission/Safety-Critical Applications. - P. Balasubramanian 001; Douglas L. Maskell (IEEE Access, 2018)

Area Optimized Quasi Delay Insensitive Majority Voter for TMR Applications. - P. Balasubramanian 001; Douglas L. Maskell; Nikos E. Mastorakis (EECS, 2019)

Generalized Majority Voter Design Method for N-Modular Redundant Systems Used in Mission- and Safety-Critical Applications. - Jaytrilok Choudhary; P. Balasubramanian 001; Danny M. Varghese; Dhirendra Pratap Singh; Douglas L. Maskell (Comput., 2019)

Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder. - P. Balasubramanian 001; Douglas L. Maskell; Nikos E. Mastorakis (CoRR, 2019)

Indicating Asynchronous Array Multipliers. - P. Balasubramanian 001; Douglas L. Maskell (CoRR, 2019)

Time-Multiplexed FPGA Overlay Architectures: A Survey. - Xiangwei Li; Douglas L. Maskell (ACM Trans. Design Autom. Electr. Syst., 2019)

Energy Efficient In-memory Integer Multiplication Based on Racetrack Memory. - Tao Luo 014; Wei Zhang 012; Bingsheng He; Cheng Liu 008; Douglas L. Maskell (ICDCS, 2020)

High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay. - Xiangwei Li; Kizheppatt Vipin; Douglas L. Maskell; Suhaib A. Fahmy; Abhishek Kumar Jain (ISCAS, 2020)

Hardware Optimized Approximate Adder with Normal Error Distribution. - Raunaq Nayar; Padmanabhan Balasubramanian; Douglas L. Maskell (ISVLSI, 2020)

An Approximate Adder with Reduced Error and Optimized Design Metrics. - Padmanabhan Balasubramanian; Raunaq Nayar; Douglas L. Maskell (APCCAS, 2021)

Image Compression using Approximate Addition. - Raunaq Nayar; Padmanabhan Balasubramanian; Douglas Leslie Maskell (TENCON, 2021)

An Approximate Adder With a Near-Normal Error Distribution: Design, Error Analysis and Practical Application. - Padmanabhan Balasubramanian; Raunaq Nayar; Douglas L. Maskell; Nikos E. Mastorakis (IEEE Access, 2021)

Gate-Level Static Approximate Adders. - P. Balasubramanian 001; Raunaq Nayar; Douglas L. Maskell (CoRR, 2021)

Approximator: A Software Tool for Automatic Generation of Approximate Arithmetic Circuits. - Padmanabhan Balasubramanian; Raunaq Nayar; Okkar Min; Douglas L. Maskell (Comput., 2022)

Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation. - Abhishek Kumar Jain; Douglas L. Maskell; Suhaib A. Fahmy (IEEE Trans. Parallel Distributed Syst., 2022)

Fault-Tolerant Design Approach Based on Approximate Computing. - P. Balasubramanian 001; Douglas L. Maskell (CoRR, 2023)

A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation. - Xiangwei Li; Douglas L. Maskell; Carol Jingyi Li; Philip H. W. Leong; David Boland (ACM Trans. Reconfigurable Technol. Syst., 2023)

A New Carry Look-Ahead Adder Architecture Enabling Improved Speed and Energy Efficiency. - Padmanabhan Balasubramanian; Douglas L. Maskell (PACRIM, 2024)

Neural Combinatorial Optimization Algorithms for Solving Vehicle Routing Problems: A Comprehensive Survey with Perspectives. - Xuan Wu 004; Di Wang 004; Lijie Wen 001; Yubin Xiao; Chunguo Wu; Yuesong Wu; Chaoyu Yu; Douglas L. Maskell; You Zhou 008 (CoRR, 2024)

Fast Bipartitioned Hybrid Adder Utilizing Carry Select and Carry Lookahead Logic. - Padmanabhan Balasubramanian; Douglas L. Maskell (CoRR, 2024)