XIRU: Interface de Rede Extensível para Integração de Núcleos a uma Rede-em-Chip. - Douglas R. Melo; Michelle S. Wangham; Cesar A. Zeferino (RITA, 2014)

A Hardware Accelerator for Anisotropic Diffusion Filtering in FPGA. - Guilherme F. Weidle; Felipe Viel; Douglas Rossi de Melo; Cesar A. Zeferino (ISCAS, 2018)

Analysis of LEON3 systems integration for a Network-on-Chip. - Lucas M. V. Pereira; Douglas R. Melo; Cesar A. Zeferino; Eduardo A. Bezerra (LATS, 2018)

Characterization of a RISC-V Microcontroller Through Fault Injection. - Dario Asciolla; Luigi Dilillo; Douglas A. dos Santos; Douglas R. Melo; Alessandra Menicucci; Marco Ottavi (ApplePies, 2019)

A Low-Cost Hardware Accelerator for CCSDS 123 Predictor in FPGA. - Lucas M. V. Pereira; Douglas A. dos Santos; Cesar A. Zeferino; Douglas R. Melo (ISCAS, 2019)

Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router. - Douglas Rossi de Melo; César Albenes Zeferino; Luigi Dilillo; Eduardo Augusto Bezerra (LATS, 2019)

Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design. - Douglas R. Melo; Cesar A. Zeferino; Luigi Dilillo; Eduardo A. Bezerra (Sensors, 2019)

A Low-Cost Fault-Tolerant RISC-V Processor for Space Systems. - Douglas Almeida dos Santos; Lucas Matana Luza; César Albenes Zeferino; Luigi Dilillo; Douglas Rossi de Melo (DTIS, 2020)

Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router. - Douglas Rossi Melo; César Albenes Zeferino; Eduardo Augusto Bezerra; Luigi Dilillo (DTIS, 2021)

Characterization of a RISC-V System-on-Chip under Neutron Radiation. - Douglas A. dos Santos; Lucas M. Luza; Maria Kastriotou; Carlo Cazzaniga; Cesar A. Zeferino; Douglas R. Melo; Luigi Dilillo (DTIS, 2021)

MPI hardware framework for many-core based embedded systems. - Rodrigo V. M. Pereira; Laio Oriel Seman; Marcelo Daniel Berejuck; Douglas Rossi de Melo; Analúcia Schiaffino Morales; Eduardo Augusto Bezerra (Int. J. Sens. Networks, 2021)

Neutron Irradiation Testing and Analysis of a Fault-Tolerant RISC-V System-on-Chip. - Douglas A. dos Santos; André Martins Pio de Mattos; Lucas M. Luza; Carlo Cazzaniga; Maria Kastriotou; Douglas R. Melo; Luigi Dilillo (DFT, 2022)

A Survey of the RISC-V Architecture Software Support. - Benjamin W. Mezger; Douglas A. dos Santos; Luigi Dilillo; Cesar A. Zeferino; Douglas R. Melo (IEEE Access, 2022)

A Low-Cost Hardware Accelerator for CCSDS 123 Lossless Hyperspectral Image Compression. - Wesley Grignani; Douglas A. dos Santos; Luigi Dilillo; Felipe Viel; Douglas R. Melo (DFT, 2023)

Implementation and Reliability Evaluation of a RISC-V Vector Extension Unit. - Carolina Imianosky; Douglas A. dos Santos; Douglas R. Melo; Felipe Viel; Luigi Dilillo (DFT, 2023)

Hardening a Real-Time Operating System for a Dependable RISC-V System-on-Chip. - Benjamin W. Mezger; Douglas A. dos Santos; Luigi Dilillo; Douglas R. Melo (DFT, 2023)

Characterization of a Fault-Tolerant RISC-V System-on-Chip for Space Environments. - Douglas A. dos Santos; André Martins Pio de Mattos; Douglas R. Melo; Luigi Dilillo (DFT, 2023)

Using HARV-SoC for Reliable Sensing Applications in Radiation Harsh Environments. - André Martins Pio de Mattos; Douglas A. dos Santos; Carolina Imianosky; Douglas R. Melo; Luigi Dilillo (IWASI, 2023)

Reliability Analysis of a Low-Cost CCSDS 123 Hyperspectral Image Compressor. - Wesley Grignani; Douglas A. dos Santos; Luigi Dilillo; Douglas R. Melo (DFT, 2024)

Implementation and Reliability Evaluation of a ChaCha20 Stream Cipher Hardware Accelerator. - Wesley Grignani; Khalil G. Queiroz de Santana; Douglas A. dos Santos; Luigi Dilillo; Douglas R. Melo (DFT, 2024)

Special Session: Reliability and Performance Evaluation of a RISC-V Vector Extension Unit for Vector Multiplication. - Carolina Imianosky; Douglas A. dos Santos; Douglas R. Melo; Felipe Viel; Luigi Dilillo (DFT, 2024)

Deep Nibble: A 4-bit Number Format for Efficient DNN Training and Inference in FPGA. - Luiz Fernando Heidrich Duarte; George B. Nardes; Wesley Grignani; Douglas R. Melo; Cesar A. Zeferino (SBCCI, 2024)

A Low-Cost Accelerator for License Plate Character Recognition Using Convolutional Neural Networks. - George B. Nardes; Thiago H. Rausch; Douglas R. Melo; Cesar A. Zeferino (LASCAS, 2025)

Hardening an AMBA-AXI Network Interface for a Reliable Network-on-Chip. - Thiago H. Rausch; Wesley Grignani; Gustavo H. S. Müller; Douglas A. dos Santos; Luigi Dilillo; Douglas R. Melo (LASCAS, 2025)

A fault-tolerant CCSDS 123 hardware accelerator for space applications. - Wesley Grignani; Felipe Viel; Douglas A. dos Santos; Luigi Dilillo; Douglas R. Melo (Integr., 2025)

A Dependable and Low-Cost CCSDS 123 Hyperspectral Image Compressor. - Wesley Grignani; Douglas A. dos Santos; Felipe Viel; Luigi Dilillo; Douglas R. Melo (IEEE Embed. Syst. Lett., 2025)