Synthesis of High Performance Extended Burst Mode Asynchronous State Machines. - Duarte Lopes de Oliveira; Marius Strum; Wang Jiang Chau; Wagner Chiepa Cunha (SBCCI, 2000)

Synthesis of Multi-Burst Controllers as Modified Huffman Machines. - Duarte Lopes de Oliveira; Wagner Chiepa Cunha; Marius Strum; Wang Jiang Chau (SBCCI, 2001)

Miriã: a CAD tool to synthesize multi-burst controllers for heterogeneous systems. - Duarte Lopes de Oliveira; Marius Strum; Jiang Chau Wang; Wagner Chiepa Cunha (Microelectron. Reliab., 2003)

Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. - Duarte Lopes de Oliveira; Marius Strum; Jiang Chau Wang (SBCCI, 2005)

Burst-Mode Asynchronous Controllers on FPGA. - Duarte Lopes de Oliveira; Marius Strum; Sandro S. Sato (Int. J. Reconfigurable Comput., 2008)

Design of locally-clocked asynchronous finite state machines using synchronous CAD tools. - Duarte Lopes de Oliveira; Diego Bompean; Tiago S. Curtinhas; Lester de Abreu Faria (LASCAS, 2013)

Design of synchronous pipeline digital systems operating in double-edge of the clock. - Duarte Lopes de Oliveira; Tiago S. Curtinhas; Lester de Abreu Faria; Leonardo Romano (LASCAS, 2013)

Design of asynchronous systems on FPGA using direct mapping and synchronous specification. - Duarte Lopes de Oliveira; Diego Bompean; Lester de Abreu Faria; Joao Luis V. Oliveira (ReConFig, 2013)

SICARELO: A tool for synthesis of locally-clocked extended burst-mode asynchronous Controllers. - Tiago S. Curtinhas; Duarte Lopes de Oliveira; Diego Bompean; Lester de Abreu Faria; Leonardo Romano (LASCAS, 2014)

Using FPGAs to implement asynchronous pipelines. - Duarte Lopes de Oliveira; Kledermon Garcia; Roberto d'Amore (LASCAS, 2014)

A novel State Assignment method for Extended Burst-Mode FSM design using Genetic Algorithm. - Tiago S. Curtinhas; Duarte Lopes de Oliveira; Lester de Abreu Faria; Osamu Saotome (SBCCI, 2014)

A novel asynchronous interface with pausible clock for partitioned synchronous modules. - Duarte Lopes de Oliveira; Tiago S. Curtinhas; Lester de Abreu Faria; Leonardo Romano (LASCAS, 2015)

Minimization and Encoding of High Performance Asynchronous State Machines Based on Genetic Algorithm. - Tiago S. Curtinhas; Tassio Cortes Cavalcante; Duarte Lopes de Oliveira; Lester de Abreu Faria; Osamu Saotome (SBCCI, 2015)

A design flow for locally-clocked XBM asynchronous state machines using synchronous CAD tools. - Duarte Lopes de Oliveira; Felipe Tuyama De Faria Barbosa; Tiago S. Curtinhas; Lester de Abreu Faria; Jocemar F. Sousa (LASCAS, 2016)

FPGA implementation of optimized XBM specifications by transformation for AFSMs. - Kledermon Garcia; Duarte Lopes de Oliveira; Roberto d'Amore; Lester de Abreu Faria; Joao Luis V. Oliveira (ReConFig, 2016)

Software-Defined Radio design based on GALS architecture for FPGAs. - Eduardo Lussari; Duarte Lopes de Oliveira; Lester de Abreu Faria; Orlando Verducci Jr. (SBCCI, 2016)

Implementation of Locally-Clocked XBM State Machines on FPGAs Using Synchronous CAD Tools. - Felipe Tuyama De Faria Barbosa; Duarte Lopes de Oliveira; Tiago S. Curtinhas; Lester de Abreu Faria; Jocemar Francisco De Souza Luciano (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A design flow of asynchronous burst-mode circuits without fundamental-mode timing assumption. - Higor A. Delsoto; Duarte Lopes de Oliveira; Lucas Moura Santana; Lester de Abreu Faria (LASCAS, 2018)

A novel state assignment method for XBM AFSMs without the essential hazard assumption. - Duarte Lopes de Oliveira; Tiago S. Curtinhas; Lucas Moura Santana; Lester de Abreu Faria (LASCAS, 2018)

FPGA implementation of high-performance asynchronous pipelines with robust control. - Duarte Lopes de Oliveira; Kledermon Garcia; Lucas Moura Santana; Lester de Abreu Faria (LASCAS, 2018)

A Novel Tool for Synthesis by Direct Mapping of Asynchronous Circuits from Extended STG Specifications. - Felipe Mendes; Tiago S. Curtinhas; Duarte Lopes de Oliveira; Higor A. Delsoto; Lester de Abreu Faria (VLSID, 2018)

A novel fully-programmable analog fuzzifier architecture for interval type-2 fuzzy controllers using current steering mirrors. - Gabriel Antonio Fanelli de Souza; Rodrigo Bispo dos Santos; Paloma Maria Silva Rocha Rizol; Duarte Lopes de Oliveira; Lester de Abreu Faria (J. Intell. Fuzzy Syst., 2018)

A State Assignment Method for Extended Burst-Mode gC Finite State Machines Based on Genetic Algorithm. - Tiago S. Curtinhas; Duarte Lopes de Oliveira; Gracieth Cavalcanti Batista; Vitor L. V. Torres; Leonardo Romano (LASCAS, 2019)

A Tools Flow for Synthesis of Asynchronous Control Circuits from Extended STG Specifications. - Higor A. Delsoto; Duarte Lopes de Oliveira; Gracieth Cavalcanti Batista; Diego A. Silva; Leonardo Romano (LASCAS, 2019)

An Implementation of Extended Burst-Mode Specifications as Quasi Delay Insensitive State Machines. - Duarte Lopes de Oliveira; Orlando Verducci Jr.; Vitor L. V. Torres; Gracieth Cavalcanti Batista; Robson L. Moreno; Leonardo Romano (LASCAS, 2019)

Implementation of DES Algorithm in New Non-Synchronous Architecture Aiming DPA Robustness. - Diego A. Silva; Orlando Verducci Jr.; Duarte Lopes de Oliveira (VLSI-SoC, 2019)

Automatic speech patterns recognition of commands using SVM and PSO. - Gracieth Cavalcanti Batista; Washington Luis Santos Silva; Duarte Lopes de Oliveira; Osamu Saotome (Multim. Tools Appl., 2019)

Synthesis of Asynchronous State Machines from Synchronous Specifications. - Duarte Lopes de Oliveira; Gabriel C. Duarte; Gracieth Cavalcanti Batista; Diego A. Silva; Leonardo Romano (LASCAS, 2020)

Implementation of Asynchronous Pipelines with QDI Template onto FPGAs Using Commercial Tools. - Duarte Lopes de Oliveira; Gabriel C. Duarte; Nicolly N. M. Cardoso; Gracieth Cavalcanti Batista (SBCCI, 2020)

A low-power asynchronous hardware implementation of a novel SVM classifier, with an application in a speech recognition system. - Gracieth Cavalcanti Batista; Duarte Lopes de Oliveira; Osamu Saotome; Washington Luis Santos Silva (Microelectron. J., 2020)

New Low-Power Architectures of Support Vector Machine Classifier for Speech Recognition System. - Gracieth Cavalcanti Batista; Duarte Lopes de Oliveira; Osamu Saotome (LASCAS, 2021)

A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global Communication. - Duarte Lopes de Oliveira; Gabriel C. Duarte; Gracieth Cavalcanti Batista (LASCAS, 2021)

Fault-Tolerant Quasi Delay Insensitive Combinational Circuits in Commercial FPGA Devices. - Orlando Verducci Jr.; Duarte Lopes de Oliveira; Robson L. Moreno (LATS, 2021)

A novel approach for the design of low-power pipelined synchronous systems operating in double-edge of the clock. - Orlando Verducci Jr.; Duarte Lopes de Oliveira; Gracieth Cavalcanti Batista; Tiago S. Curtinhas (Microelectron. J., 2021)

Design of Asynchronous Pipelines with QDI Template Using Commercial FPGA. - Gabriel C. Duarte; Duarte Lopes de Oliveira; Gracieth Cavalcanti Batista (LASCAS, 2022)

Fault-Tolerant Finite State Machine Quasi Delay Insensitive in Commercial FPGA Devices. - Orlando Verducci Jr.; Duarte Lopes de Oliveira; Gracieth Cavalcanti Batista (LASCAS, 2022)

Design of Quasi Delay Insensitive Combinational Circuits Based on Optimized DIMS. - Duarte Lopes de Oliveira; Marcus H. Victor; Luiz C. Moreira; Felipe F. Nascimento (LASCAS, 2023)