An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme. - Kyu-Hyoun Kim; Uksong Kang; Hoeju Chung; Dukha Park; Woo-Seop Kim; Young-Chan Jang; Moon-Sook Park; Hoon Lee; Jinyoung Kim; Jung Sunwoo; Hwan-Wook Park; Hyun-Kyung Kim; et al. (ISSCC, 2006)

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology. - Uksong Kang; Hoeju Chung; Seongmoo Heo; Dukha Park; Hoon Lee; Jin Ho Kim; Soon-Hong Ahn; Sooho Cha; Jaesung Ahn; Dukmin Kwon; Jae-Wook Lee 007; Han-Sung Joo; et al. (IEEE J. Solid State Circuits, 2010)

A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency. - Ki-Whan Song; Jinyoung Kim; Jae-Man Yoon; Sua Kim; Huijung Kim; Hyun-Woo Chung; Hyungi Kim; Kanguk Kim; Hwan-Wook Park; Hyun Chul Kang; Nam-Kyun Tak; Dukha Park; et al. (IEEE J. Solid State Circuits, 2010)

A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power. - Kyung-Soo Ha; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; Jin-Hun Jang; Hyong-Ryol Hwang; Hyung-Joon Chi; Junghwan Park; Seungjun Shin; Dukha Park; Sang-Yun Kim 001; Sukhyun Lim; et al. (ISSCC, 2019)

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process. - Hyung-Joon Chi; Chang-Kyo Lee; Junghwan Park; Jin-Seok Heo; Jaehoon Jung; Dongkeon Lee; Dae-Hyun Kim 003; Dukha Park; Kihan Kim; Sang-Yun Kim 001; Jinsol Park; Hyunyoon Cho; et al. (ISSCC, 2020)

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques. - Kyung-Soo Ha; Seungseob Lee; Youn-Sik Park; Hyuck-Joon Kwon; Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Kwang-Il Park; Jung-Bae Lee; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; et al. (IEEE J. Solid State Circuits, 2020)

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques. - Chang-Kyo Lee; Hyung-Joon Chi; Jin-Seok Heo; Junghwan Park; Jin-Hun Jang; Dongkeon Lee; Jaehoon Jung; Dong-Hun Lee; Dae-Hyun Kim 003; Kihan Kim; Sang-Yun Kim 001; Dukha Park; et al. (IEEE J. Solid State Circuits, 2021)