Design and Implementation of a 2-level FSK Digital Modems Using CORDIC Algorithm. - Xiaoxin Cui; Dunshan Yu; Shimin Sheng; Xiaole Cui (APCCAS, 2006)

A CMOS Differential Difference Amplifier with Reduced Nonlinearity Error of Interpolation for Interpolating ADCs. - Xin Zhang; Dunshan Yu; Shimin Sheng (APCCAS, 2006)

A Discrete STFT Processor for Real-time Spectrum Analysis. - Shiqun Zhang; Dunshan Yu; Shimin Sheng (APCCAS, 2006)

An Efficient VLSI Implementation of Distributed Architecture for DWT. - Xixin Cao; Qingqing Xie; Chungan Peng; Qingchun Wang; Dunshan Yu (MMSP, 2006)

Application-Dependent Interconnect Testing of Xilinx FPGAs Based on Line Branches Partitioning. - Teng Lin; Jianhua Feng; Dunshan Yu (IEICE Trans. Inf. Syst., 2009)

A Low Cost Correlator Structure in the Pseudo-Noise Code Acquisition System. - WeiJun Lu; Ying Li; Dunshan Yu; Xing Zhang (IEICE Trans. Commun., 2009)

A JTAG-based configuration circuit applied in SerDes chip. - Xun Jiang; Xiaoxin Cui; Dunshan Yu (ASICON, 2011)

A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs. - Xiaoxin Cui; Kaisheng Ma; Kai Liao; Nan Liao; Di Wu; Wei Wei; Rui Li; Dunshan Yu (ISCAS, 2013)

Design of a Reconfigurable Acoustic Modem for Underwater Sensor Networks. - Lingjuan Wu; Ryan Kastner; Bo Gu; Dunshan Yu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A Low-noise High-voltage Interface Circuit for capacitive MEMS gyroscope. - Ran Fang; Wengao Lu; Guannan Wang; Tingting Tao; Yacong Zhang; Zhongjian Chen; Dunshan Yu (J. Circuits Syst. Comput., 2013)

A capacitive Interface Circuit with capacitor mismatch Auto-compensation for MEMS gyroscope. - Ran Fang; Wengao Lu; Guannan Wang; Tingting Tao; Yacong Zhang; Zhongjian Chen; Dunshan Yu (J. Circuits Syst. Comput., 2013)

High-speed constant-time division module for Elliptic Curve Cryptography based on GF(2m). - Kai Liao; Xiaoxin Cui; Nan Liao; Tian Wang; Xiao Zhang; Ying Huang; Dunshan Yu (ISCAS, 2014)

Low power adiabatic logic based on FinFETs. - Nan Liao; Xiaoxin Cui; Kai Liao; Kaisheng Ma; Di Wu; Wei Wei; Rui Li; Dunshan Yu (Sci. China Inf. Sci., 2014)

Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs. - Kai Liao; Xiaoxin Cui; Nan Liao; Kaisheng Ma; Di Wu; Wei Wei; Rui Li; Dunshan Yu (Sci. China Inf. Sci., 2014)

Resource-efficient acquisition architecture for BOC-modulated signals. - Dengyun Lei; Weijun Lu; Dunshan Yu (IEICE Electron. Express, 2014)

Effective PPS Signal Generation with Predictive Synchronous Loop for GPS. - Yanbin Zhang; WeiJun Lu; Dengyun Lei; Yongcan Huang; Dunshan Yu (IEICE Trans. Commun., 2014)

A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications. - Nan Liao; Xiaoxin Cui; Tian Wang; Kai Liao; Yewen Ni; Dunshan Yu; Xiaole Cui (ASICON, 2015)

Employing the mixed FBB/RBB in the design of FinFET logic gates. - Tian Wang; Xiaoxin Cui; Kai Liao; Nan Liao; Yewen Ni; Dunshan Yu; Xiaole Cui (ASICON, 2015)

Key characterization factors of accurate power modeling for FinFET circuits. - Kaisheng Ma; Xiaoxin Cui; Kai Liao; Nan Liao; Di Wu; Dunshan Yu (Sci. China Inf. Sci., 2015)

Balance Differential Coherent Bit Synchronization Algorithm for GNSS Receiver. - Dengyun Lei; Weijun Lu; Yanbin Zhang; Dunshan Yu (IEICE Trans. Commun., 2015)

Improving tracking accuracy with subcarrier assistance and code monitoring for BOC modulated signal. - Yanbin Zhang; Weijun Lu; Ruiyuan Liu; Dunshan Yu (Comput. Electr. Eng., 2016)

Ultralow-power high-speed flip-flop based on multimode FinFETs. - Kai Liao; Xiaoxin Cui; Nan Liao; Tian Wang; Dunshan Yu; Xiaole Cui (Sci. China Inf. Sci., 2016)

Efficient Weak Signals Acquisition Strategy for GNSS Receivers. - Weijun Lu; Yanbin Zhang; Dengyun Lei; Dunshan Yu (IEICE Trans. Commun., 2016)

Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology. - Tian Wang; Xiaoxin Cui; Kai Liao; Nan Liao; Xiaole Cui; Dunshan Yu (IEICE Trans. Electron., 2016)

A practical cold boot attack on RSA private keys. - Tian Wang; Xiaoxin Cui; Yewen Ni; Dunshan Yu; Xiaole Cui; Gang Qu 001 (AsianHOST, 2017)

Improving DFA attacks on AES with unknown and random faults. - Nan Liao; Xiaoxin Cui; Kai Liao; Tian Wang; Dunshan Yu; Xiaole Cui (Sci. China Inf. Sci., 2017)

High-Performance Noninvasive Side-Channel Attack Resistant ECC Coprocessor for GF(2m ). - Kai Liao; Xiaoxin Cui; Nan Liao; Tian Wang; Dunshan Yu; Xiaole Cui (IEEE Trans. Ind. Electron., 2017)

Polymorphic gate based IC watermarking techniques. - Tian Wang; Xiaoxin Cui; Dunshan Yu; Omid Aramoon; Timothy Dunlap; Gang Qu 001; Xiaole Cui (ASP-DAC, 2018)

A Novel Polymorphic Gate Based Circuit Fingerprinting Technique. - Tian Wang; Xiaoxin Cui; Dunshan Yu; Omid Aramoon; Timothy Dunlap; Gang Qu 001; Xiaole Cui (ACM Great Lakes Symposium on VLSI, 2018)

A 108fsrms 0.45mW 100MS/s 1.25MHz bandwidth multi-bit ΔΣ time-to-digital converter with dynamic element matching. - Yinxuan Lyu; Jianhua Feng; Chenfeng Tu; Linqi Shi; Hongfei Ye; Weixin Gai; Dunshan Yu (ISCAS, 2018)

Design of Low-Power High-Performance FinFET Standard Cells. - Tian Wang; Xiaoxin Cui; Kai Liao; Nan Liao; Dunshan Yu; Xiaole Cui (Circuits Syst. Signal Process., 2018)

Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits. - Tian Wang; Xiaoxin Cui; Yewen Ni; Dunshan Yu; Xiaole Cui (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Improved Discrete Wavelet Analysis and Principal Component Analysis for EEG Signal Processing. - Yi-Hsiang Chen; Xiaoxin Cui; Kanglin Xiao; Dunshan Yu (ASICON, 2019)

Designing a 3D Graphics Processor for Mobile Applications. - Lingjuan Wu; Wenqian Zhao; Dunshan Yu (ASICON, 2019)

Perceptual Fast CU Size Decision Algorithm for AVS2 Intra Coding. - Hao Xie; Guoqing Xiang; Dunshan Yu; Hong Yu 019; Yuan Li 014; Wei Yan (BigMM, 2019)

FPGA Implementation of Quantized Convolutional Neural Networks. - Qi Zhang; Jian Cao; Ying Zhang; Shiguang Zhang; Quan Zhang; Dunshan Yu (ICCT, 2019)

Multimodal Emotion Recognition Model using Physiological Signals. - Yuxuan Zhao 002; Xinyan Cao; Jinlong Lin; Dunshan Yu; Xixin Cao (CoRR, 2019)

A New Method for Futures Price Trends Forecasting Based on BPNN and Structuring Data. - Weijun Lu; Chao Geng; Dunshan Yu (IEICE Trans. Inf. Syst., 2019)

A 3D Convolutional Neural Network for Emotion Recognition based on EEG Signals. - Yuxuan Zhao 002; Jin Yang; Jinlong Lin; Dunshan Yu; Xixin Cao (IJCNN, 2020)

Fully on-chip clock jitter and skew measurement scheme via incoherent subsampling. - Yinxuan Lyu; Jianhua Feng; Kai Zhu; Hongfei Ye; Dunshan Yu (Microelectron. J., 2020)

A Novel Circuit Authentication Scheme Based on Partial Polymorphic Gates. - Timothy Dunlap; Omid Aramoon; Gang Qu 001; Tian Wang; Xiaoxin Cui; Dunshan Yu (AsianHOST, 2021)

Low Power Readout Integrated Circuit with PFM-based ADCs Employing Residue Quantization for Uncooled Infrared Imagers. - Ye Zhou; Shanzhe Yu; Wengao Lu; Dunshan Yu; Yacong Zhang; Zhongjian Chen (ASICON, 2021)

A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations. - Yisong Kuang; Xiaoxin Cui; Yi Zhong; Kefei Liu 002; Chenglong Zou; Zhenhui Dai; Dunshan Yu; Yuan Wang 001; Ru Huang 001 (ISCAS, 2021)

A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS. - Yisong Kuang; Xiaoxin Cui; Yi Zhong; Kefei Liu 002; Chenglong Zou; Zhenhui Dai; Yuan Wang 001; Dunshan Yu; Ru Huang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

An Event-driven Spiking Neural Network Accelerator with On-chip Sparse Weight. - Yisong Kuang; Xiaoxin Cui; Chenglong Zou; Yi Zhong; Zhenhui Dai; Zilin Wang; Kefei Liu 002; Dunshan Yu; Yuan Wang 001 (ISCAS, 2022)

ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator. - Yisong Kuang; Xiaoxin Cui; Zilin Wang; Chenglong Zou; Yi Zhong; Kefei Liu 002; Zhenhui Dai; Dunshan Yu; Yuan Wang 001; Ru Huang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Multimodal Affective States Recognition Based on Multiscale CNNs and Biologically Inspired Decision Fusion Model. - Yuxuan Zhao 002; Xinyan Cao; Jinlong Lin; Dunshan Yu; Xixin Cao (IEEE Trans. Affect. Comput., 2023)

A multichannel readout integrated circuit with column-wise pseudo differential extended counting ADCs for an uncooled infrared focal plane array based on silicon diodes. - Ye Zhou; Wengao Lu; Shanzhe Yu; Dunshan Yu; Yacong Zhang; Zhongjian Chen (Microelectron. J., 2023)

An Efficient Spiking Convolutional Architecture with Compressed Address Event Representation and Adaptive Delay Asynchronous Clocks. - Zhenhui Dai; Li Lun; Zilin Wang; Jiawei Wang; Kunyu Feng; Yuan Wang 001; Dunshan Yu; Xiaoxin Cui (BioCAS, 2024)

An Energy-Efficient Differential Frame Convolutional Accelerator with on-Chip Fusion Storage Architecture and Pixel-Level Pipeline Data Flow. - Zhenhui Dai; Jiawei Wang; Yi Zhong; Kunyu Feng; Cheng Zhao; Yuanyuan Jiang; Peiyu Chen; Yuan Wang 001; Dunshan Yu; Xiaoxin Cui (ISCAS, 2024)

Towards Effective and Sparse Adversarial Attack on Spiking Neural Networks via Breaking Invisible Surrogate Gradients. - Li Lun; Kunyu Feng; Qinglong Ni; Ling Liang; Yuan Wang 001; Ying Li 056; Dunshan Yu; Xiaoxin Cui (CVPR, 2025)

A Compact Full Pipeline Architecture of SM3 Algorithm with High throughput and High Efficiency. - Tuo Li; Chao Cheng; Changhong Wang; Ruiting Wang; Xiaofeng Zou; Dunshan Yu (ISCAS, 2025)

A 64Gb/s/wire 10.5Tb/s/mm/Layer Single-Ended Simultaneous Bi-Directional Transceiver with Echo and Crosstalk Cancellation for a Die-to-Die Interface in 28nm CMOS. - Zhifei Wang; Zhiwen Huang; Tianchen Ye; Bingyi Ye; Fangzhu Li; Wei Wang; Dunshan Yu; Weixin Gai (ISSCC, 2025)

25.5 A 99.5mW/Port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS. - Guangdong Wu; Yuanliang Li; Bingyi Ye; Fangzhu Li; Xin Liu; Haowei Niu; Ruixu Wang; Dunshan Yu; Weixin Gai (ISSCC, 2025)

A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS. - Bingyi Ye; Tianchen Ye; Tianyuan Zhong; Zhiwen Huang; Lei Shen; Boyang Zhang; Dunshan Yu; Yandong He; Weixin Gai (ISSCC, 2025)