A compact adaptive equalizer IC for HIPERLAN system. - Jinn-Shyan Wang; Pei-Lung Lin; Wern-Ho Sheen; Duo Sheng; Yu-Ming Huang (ISCAS, 2000)

Design of a 3-V 300-MHz low-power 8-b×8-b pipelined multiplier using pulse-triggered TSPC flip-flops. - Jinn-Shyan Wang; Po-Hui Yang; Duo Sheng (IEEE J. Solid State Circuits, 2000)

A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications. - Duo Sheng; Ching-Che Chung; Chen-Yi Lee (APCCAS, 2006)

An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications. - Duo Sheng; Ching-Che Chung; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

An all digital spread spectrum clock generator with programmable spread ratio for SoC applications. - Duo Sheng; Ching-Che Chung; Chen-Yi Lee (APCCAS, 2008)

Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications. - Duo Sheng; Ching-Che Chung; Chen-Yi Lee (IEICE Electron. Express, 2010)

A 600kHz to 1.2GHz all-digital delay-locked loop in 65nm CMOS technology. - Ching-Che Chung; Duo Sheng; Chia-Lin Chang (IEICE Electron. Express, 2011)

A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology. - Ching-Che Chung; Duo Sheng; Sung-En Shen (IEICE Electron. Express, 2011)

A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications. - Duo Sheng; Ching-Che Chung; Chen-Yi Lee (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A low-power and small-area all-digital spread-spectrum clock generator in 65nm CMOS technology. - Ching-Che Chung; Duo Sheng; Wei-Da Ho (VLSI-DAT, 2012)

A high-performance wear-leveling algorithm for flash memory system. - Ching-Che Chung; Duo Sheng; Ning-Mi Hsueh (IEICE Electron. Express, 2012)

An All-Digital Large-N Audio Frequency Synthesizer for HDMI Applications. - Ching-Che Chung; Duo Sheng; Chia-Lin Chang; Wei-Da Ho; Yang-Di Lin; Fang-Nien Lu (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A high-resolution and one-cycle conversion time-to-digital converter architecture for PET image applications. - Duo Sheng; Ching-Che Chung; Chih-Chung Huang; Jia-Wei Jian (EMBC, 2013)

A 0.5V/1.0V fast lock-in ADPLL for DVFS battery-powered devices. - Ching-Che Chung; Duo Sheng; Wei-Siang Su (VLSI-DAT, 2013)

A counter-based all-digital spread-spectrum clock generator with high EMI reduction in 65nm CMOS. - Ching-Che Chung; Duo Sheng; Wei-Da Ho (IEICE Electron. Express, 2013)

An all-digital phase-locked loop compiler with liberty timing files. - Ching-Che Chung; Duo Sheng; Chen-Han Chen (VLSI-DAT, 2014)

High-resolution and all-digital on-chip delay measurement with low supply sensitivity for SoC applications. - Duo Sheng; Ching-Che Chung; Hsiu-Fan Lai; Shu-Syun Jhao (IEICE Electron. Express, 2014)

High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology. - Ching-Che Chung; Duo Sheng; Sung-En Shen (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A High Resolution On-Chip Delay Sensor with Low Supply-Voltage Sensitivity for High-Performance Electronic Systems. - Duo Sheng; Hsiu-Fan Lai; Sheng-Min Chan; Min-Rong Hong (Sensors, 2015)

A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator. - Ching-Che Chung; Duo Sheng; Wei-Da Ho (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A Wide-Range Low-Cost All-Digital Duty-Cycle Corrector. - Ching-Che Chung; Duo Sheng; Chang-Jun Li (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node. - Duo Sheng; Min-Rong Hong (Sensors, 2016)

A fast phase tracking reference-less all-digital CDR circuit for human body channel communication. - Ching-Che Chung; Duo Sheng; Ming-Chieh Li; Yi-Che Tsai (Microelectron. J., 2019)

High-Timing-Resolution and Low-Complexity Cell-Based Digitally Controlled Oscillator. - Duo Sheng; Wei-Yen Chen; Yu-Hsiang Chang; Hao-Ting Huang (ICCE-TW, 2020)

Design of a human body channel communication transceiver using convolutional codes. - Ching-Che Chung; Duo Sheng; Ming-Hsuan Li (Microelectron. J., 2020)

High-Resolution All-Digital Transmit Beamformer for High-Frequency and Wearable Ultrasound Imaging Systems. - Duo Sheng; Jun-Wei Lin; Yi-Hsiang Wang; Chih-Chung Huang (IEEE Trans. Very Large Scale Integr. Syst., 2020)

DLL-Based Transmit Beamforming IC for High -Frequency Ultrasound Medical Imaging System. - Duo Sheng; Chih-Hao Liu; Sih-Ying Chen; Bin-Yang Song; Ying-Chi Chiu; Ming-Han Cai (ICCE-TW, 2021)

Digitally Controlled Oscillator with High Timing Resolution and Low Complexity for Clock Generation. - Duo Sheng; Wei-Yen Chen; Hao-Ting Huang; Li Tai (Sensors, 2021)

A Digital Receive Beamforming IC for High-Frequency Ultrasound Imaging System. - Duo Sheng; Ying-Chi Chiu; Yun-Quan Li; You-Ning Lo; Chao-Kai Pai; Ten-Ling Wang (ASICON, 2023)

Low-Jitter Frequency Doubling Circuit Supporting Higher-Speed BISG and Aging Sensing in a Chiplet-Based Design Environment. - Ko-Hong Lin; Ont-Derh Lin; Shi-Yu Huang; Duo Sheng (IEEE Trans. Very Large Scale Integr. Syst., 2024)

An All-Digital Capacitance-to-Digital Converter Based on Time-to-Digital Converter. - Duo Sheng; Chao-Kai Pai; Yi-Ju Chen; Bo-An Chen; Hao-Yuan Cheng; Ke-Jhong Tan; Ri-En Yeh (ICEIC, 2025)