Design and performance evaluation of a 2D-mesh Network on Chip prototype using FPGA. - Luofeng Geng; Gaoming Du; Duoli Zhang; Minglun Gao; Ning Hou; Yu-Kun Song (APCCAS, 2008)

A technique of automatic monitor generation based on FSM. - Duoli Zhang; Yu-Kun Song; Gaoming Du; Yuanjie Zhai (APCCAS, 2008)

Scalability Study on Mesh Based Network on Chip. - Gaoming Du; Duoli Zhang; Yu-Kun Song; Minglun Gao; Luofeng Geng; Ning Hou (PACIIA (2), 2008)

VLSI Architecture of Video Post-Processing System for MPEG/H.26X. - Chun-Ping Qin; Duoli Zhang; Gaoming Du; Minglun Gao; Yu-Kun Song (NCM, 2009)

Application-level pipelining on Hierarchical NoC. - Wei Yi; Hongbing Pan; Peng Pan; Li Li 003; Minglun Gao; Ning Hou; Gaoming Du; Duoli Zhang (ISCAS, 2010)

Meshim: A high-level performance simulation platform for three-dimensional network-on-chip. - Menwang Xie; Duoli Zhang; Yao Li (ASICON, 2011)

Performance analysis for matrix-multiplication based on an heterogeneous multi-core SoC. - Yu-Kun Song; Rui Jiao; Duoli Zhang; Dongxue Gao (ASICON, 2015)

Design and implementation of homogeneous multi-core system. - Xiaolei Wang; Dongming Qu; Yu-Kun Song; Duoli Zhang (ASICON, 2017)

A chain-multiplier for large scale matrix multiplication. - Can Wei; Yu-Kun Song; Duoli Zhang (ASICON, 2017)

On the Accuracy of Stochastic Delay Bound for Network on Chip. - Gaoming Du; Yongliang Zhang; Zhenmin Li; Guanyu Liu; Duoli Zhang; Yiming Ouyang (NOCS, 2017)

Efficient Softmax Hardware Architecture for Deep Neural Networks. - Gaoming Du; Chao Tian; Zhenmin Li; Duoli Zhang; Yongsheng Yin; Yiming Ouyang (ACM Great Lakes Symposium on VLSI, 2019)

NR-MPA: Non-Recovery Compression Based Multi-Path Packet-Connected-Circuit Architecture of Convolution Neural Networks Accelerator. - Gaoming Du; Zhenwen Yang; Zhenmin Li; Duoli Zhang; Yongsheng Yin; Zhonghai Lu (ICCD, 2019)

SSS: Self-aware System-on-chip Using a Static-dynamic Hybrid Method. - Gaoming Du; Guanyu Liu; Zhenmin Li; Yifan Cao; Duoli Zhang; Yiming Ouyang; Minglun Gao; Zhonghai Lu (ACM J. Emerg. Technol. Comput. Syst., 2019)

A low-latency DMM-1 encoder for 3D-HEVC. - Gaoming Du; Yifan Cao; Zhenmin Li; Duoli Zhang; Li Wang; Yu-Kun Song; Yiming Ouyang (J. Real Time Image Process., 2020)

Design and Implementation of A High-speed Configurable 2D ML-CFAR Detector. - Xiangying Tao; Duoli Zhang; Min Wang; Yan Ma; Yukun Song (ASICON, 2021)

A Real-Time Effective Fusion-Based Image Defogging Architecture on FPGA. - Gaoming Du; Jiting Wu; Hongfang Cao; Kun Xing; Zhenmin Li; Duoli Zhang; Xiaolei Wang (ACM Trans. Multim. Comput. Commun. Appl., 2021)

RB-OLITS: A Worst Case Reorder Buffer Size Reduction Approach for 3-D-NoC. - Zhenmin Li; Yuqing Ma; Gaoming Du; Xiaolei Wang; Yukun Song; Duoli Zhang (IEEE Des. Test, 2022)

A communication-aware and predictive list scheduling algorithm for network-on-chip based heterogeneous muti-processor system-on-chip. - Yu Yao; Yukun Song; Hu Ge; Ying Huang; Duoli Zhang (Microelectron. J., 2022)

A Memory-Constraint-Aware List Scheduling Algorithm for Memory-Constraint Heterogeneous Muti-Processor System. - Yu Yao; Yukun Song; Ying Huang; Wei Ni; Duoli Zhang (IEEE Trans. Parallel Distributed Syst., 2023)

A Low-Latency Polynomial Multiplier Accelerator for CRYSTALS-Dilithium Digital Signature. - Gaoming Du; Zhuo Chen; Zhenmin Li; Xiaolei Wang; Duoli Zhang (ACM Great Lakes Symposium on VLSI, 2024)

An Efficient Ring Polynomial Multiplication Accelerator for Homomorphic Encryption. - Jingwei Ren; Gaoming Du; Zhenmin Li; Xianhu Jia; Qiuzhu Liao; Xiaolei Wang; Duoli Zhang (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

An efficient dehazing accelerator by fusing dark channel prior and guided filter. - Tianyi Lv; Wei Mao; Zhenmin Li; Gaoming Du; Xiaolei Wang; Wei Ni; Duoli Zhang (Microelectron. J., 2025)