Resource efficient implementation of T-Boxes in AES on Virtex-5 FPGA. - Dur-e-Shahwar Kundi; Arshad Aziz; Nassar Ikram (Inf. Process. Lett., 2010)

Software implementation of Standard Hash Algorithm (SHA-3) Keccak on Intel core-i5 and Cavium Networks Octeon Plus embedded platform. - Aisha Malik; Arshad Aziz; Dur-e-Shahwar Kundi; Moiz Akhter (MECO, 2013)

An efficient single unit T-box/T-1-box implementation for 128-bit AES on FPGA. - Dur-e-Shahwar Kundi; Arshad Aziz; Majida Kazmi (Secur. Commun. Networks, 2015)

A low-power SHA-3 designs using embedded digital signal processing slice on FPGA. - Dur-e-Shahwar Kundi; Arshad Aziz (Comput. Electr. Eng., 2016)

A high performance ST-Box based unified AES encryption/decryption architecture on FPGA. - Dur-e-Shahwar Kundi; Arshad Aziz; Nassar Ikram (Microprocess. Microsystems, 2016)

Non Sub-sampled Contourlet Transform Based Feature Extraction Technique for Differentiating Glioma Grades Using MRI Images. - Razia Zia; Pervez Akhtar; Arshad Aziz; Maroof Ali Shah; Dur-e-Shahwar Kundi (Australasian Conference on Artificial Intelligence, 2017)

Multi-resolution transforms-based hybrid feature extraction technique for differentiating glioma grades. - Razia Zia; Pervez Akhtar; Arshad Aziz; Dur-e-Shahwar Kundi (Int. J. Wavelets Multiresolution Inf. Process., 2018)

A Pareto-Optimal Multi-filter Architecture on FPGA for Image Processing Applications. - Majida Kazmi; Arshad Aziz; Dur-e-Shahwar Kundi (Circuits Syst. Signal Process., 2019)

AxMM: Area and Power Efficient Approximate Modular Multiplier for R-LWE Cryptosystem. - Dur-e-Shahwar Kundi; Song Bian 001; Ayesha Khalid; Chenghua Wang; Máire O'Neill; Weiqiang Liu 001 (ISCAS, 2020)

Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3. - Dur-e-Shahwar Kundi; Ayesha Khalid; Arshad Aziz; Chenghua Wang; Máire O'Neill; Weiqiang Liu 001 (IEEE Trans. Circuits Syst., 2020)

An Efficient and Parallel R-LWE Cryptoprocessor. - Yuqing Zhang; Chenghua Wang; Dur-e-Shahwar Kundi; Ayesha Khalid; Máire O'Neill; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

High-Performance Systolic Array Montgomery Multiplier for SIKE. - Ziying Ni; Dur-e-Shahwar Kundi; Máire O'Neill; Weiqiang Liu 001 (ISCAS, 2021)

Towards CRYSTALS-Kyber: A M-LWE Cryptoprocessor with Area-Time Trade-Off. - Kan Yao; Dur-e-Shahwar Kundi; Chenghua Wang; Máire O'Neill; Weiqiang Liu 001 (ISCAS, 2021)

APAS: Application-Specific Accelerators for RLWE-Based Homomorphic Linear Transformations. - Song Bian 001; Dur-e-Shahwar Kundi; Kazuma Hirozawa; Weiqiang Liu 001; Takashi Sato 001 (IEEE Trans. Inf. Forensics Secur., 2021)

Approximate Computing for Cryptography. - Dur-e-Shahwar Kundi; Ayesha Khalid; Song Bian 001; Weiqiang Liu 001 (Approximate Computing, 2022)

Stacked Ensemble Models Evaluation on DL Based SCA. - Anh-Tuan Hoang; Neil Hanley; Ayesha Khalid; Dur-e-Shahwar Kundi; Máire O'Neill (ICSBT/SECRYPT (Revised Selected Papers), 2022)

Horizontal Correlation Analysis without Precise Location on Schoolbook Polynomial Multiplication of Lattice-based Cryptosystem. - Chuanchao Lu; Yijun Cui; Yang Li; Dur-e-Shahwar Kundi; Chenghua Wang; Weiqiang Liu 001 (ISCAS, 2022)

A Lightweight and Efficient Schoolbook Polynomial Multiplier for Saber. - Yuantuo Zhang; Yijun Cui; Ziying Ni; Dur-e-Shahwar Kundi; Dongsheng Liu; Weiqiang Liu 001 (ISCAS, 2022)

Stacked Ensemble Model for Enhancing the DL based SCA. - Anh-Tuan Hoang; Neil Hanley; Ayesha Khalid; Dur-e-Shahwar Kundi; Máire O'Neill (SECRYPT, 2022)

Efficient Pipelining Exploration for A High-performance CRYSTALS-Kyber Accelerator. - Ziying Ni; Ayesha Khalid; Dur-e-Shahwar Kundi; Máire O'Neill; Weiqiang Liu 001 (IACR Cryptol. ePrint Arch., 2022)

AxRLWE: A Multilevel Approximate Ring-LWE Co-Processor for Lightweight IoT Applications. - Dur-e-Shahwar Kundi; Ayesha Khalid; Song Bian 001; Chenghua Wang; Máire O'Neill; Weiqiang Liu 001 (IEEE Internet Things J., 2022)

A High Performance SIKE Accelerator With High Frequency and Low Area-Time Product. - Ziying Ni; Dur-e-Shahwar Kundi; Máire O'Neill; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Ultra High-Speed Polynomial Multiplications for Lattice-Based Cryptography on FPGAs. - Dur-e-Shahwar Kundi; Yuqing Zhang; Chenghua Wang; Ayesha Khalid; Máire O'Neill; Weiqiang Liu 001 (IEEE Trans. Emerg. Top. Comput., 2022)

A High-Performance SIKE Hardware Accelerator. - Ziying Ni; Dur-e-Shahwar Kundi; Máire O'Neill; Weiqiang Liu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

HPKA: A High-Performance CRYSTALS-Kyber Accelerator Exploring Efficient Pipelining. - Ziying Ni; Ayesha Khalid; Dur-e-Shahwar Kundi; Máire O'Neill; Weiqiang Liu 001 (IEEE Trans. Computers, 2023)

High-Performance NTT Hardware Accelerator to Support ML-KEM and ML-DSA. - Dur-e-Shahwar Kundi; Jose Maria Bermudo Mera; Pierre-Yves Strub; Michael Hutter (ASHES@CCS, 2024)