A Note on 5-bit Quadratic Permutations' Classification. - Dusan Bozilov; Begül Bilgin; Haci Ali Sahin (IACR Trans. Symmetric Cryptol., 2017)

Teaching HW/SW codesign with a Zynq ARM/FPGA SoC. - Josep Balasch; Arthur Beckers; Dusan Bozilov; Sujoy Sinha Roy; Furkan Turan; Ingrid Verbauwhede (EWME, 2018)

Optimized Threshold Implementations: Minimizing the Latency of Secure Cryptographic Accelerators. - Dusan Bozilov; Miroslav Knezevic; Ventzislav Nikov (CARDIS, 2019)

Design Trade-offs in Threshold Implementations. - Dusan Bozilov; Ventzislav Nikov; Vincent Rijmen (ICECS, 2019)

PRINCEv2 - More Security for (Almost) No Overhead. - Dusan Bozilov; Maria Eichlseder; Miroslav Knezevic; Baptiste Lambin; Gregor Leander; Thorben Moos; Ventzislav Nikov; Shahram Rasoolzadeh; Yosuke Todo; Friedrich Wiemer (SAC, 2020)

On Optimality of d + 1 TI Shared Functions of 8 Bits or Less. - Dusan Bozilov (IACR Cryptol. ePrint Arch., 2020)

New First-Order Secure AES Performance Records. - Aein Rezaei Shahmirzadi; Dusan Bozilov; Amir Moradi 001 (IACR Cryptol. ePrint Arch., 2021)

Optimized threshold implementations: securing cryptographic accelerators for low-energy and low-latency applications. - Dusan Bozilov; Miroslav Knezevic; Ventzislav Nikov (J. Cryptogr. Eng., 2022)