24 GHz Low-Noise Amplifiers using High Q Series-Stub Transmission Lines in 0.18µm CMOS. - Dustin Dunwell; Brian Frank (CCECE, 2006)

Computer design of super-orthogonal space-time trellis codes. - Michael Bale; Brady Laska; Dustin Dunwell; François Chan; Hamid Jafarkhani (IEEE Trans. Wirel. Commun., 2007)

Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiver. - Dustin Dunwell; Anthony Chan Carusone (CICC, 2010)

A 15-Gb/s preamplifier with 10-dB gain control and 8-mV sensitivity in 65-nm CMOS. - Dustin Dunwell; Anthony Chan Carusone (ISCAS, 2010)

A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on. - Dustin Dunwell; Anthony Chan Carusone; Jared Zerbe; Brian S. Leibowitz; Barry Daly; John C. Eble (CICC, 2012)

Channel characterization using jitter measurements. - Dustin Dunwell; Atul Gupta; Anthony Chan Carusone (ISCAS, 2013)

Modeling Oscillator Injection Locking Using the Phase Domain Response. - Dustin Dunwell; Anthony Chan Carusone (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC. - Mike Bichan; Dustin Dunwell; Qiwei Wang; Anthony Chan Carusone (ISCAS, 2014)

All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters. - Shuai Chen; Luke Wang; Hong Zhang 009; Rosanah Murugesu; Dustin Dunwell; Anthony Chan Carusone (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS. - Shayan Shahramian; Behzad Dehlaghi; Joshua Liang; Ryan Bespalko; Dustin Dunwell; James Bailey 002; Bo Wang; Alireza Sharif Bakhtiar; Michael O'Farrell; Kerry Tang; Anthony Chan Carusone; David Cassan; et al. (ISSCC, 2019)

Co-Design of Interchiplet, Package, and System Interconnect Protocols. - Tony Chan Carusone; Dustin Dunwell; Sundeep Gupta; Letizia Giuliano; Adrien Auge; Michael Klempa; Sue Hung Fung (IEEE Micro, 2025)