A FPGA design for high speed feature extraction from a compressed measurement stream. - Dustin Richmond; Ryan Kastner; Ali Irturk; John McGarry (FPL, 2013)

Real-time 3D reconstruction for FPGAs: A case study for evaluating the performance, area, and programmability trade-offs of the Altera OpenCL SDK. - Quentin Gautier; Alexandria Shearer; Janarbek Matai; Dustin Richmond; Pingfan Meng; Ryan Kastner (FPT, 2014)

Enabling FPGAs for the Masses. - Janarbek Matai; Dustin Richmond; Dajung Lee; Ryan Kastner (CoRR, 2014)

RIFFA 2.1: A Reusable Integration Framework for FPGA Accelerators. - Matthew Jacobsen; Dustin Richmond; Matthew Hogains; Ryan Kastner (ACM Trans. Reconfigurable Technol. Syst., 2015)

Tinker: Generating Custom Memory Architectures for Altera's OpenCL Compiler. - Dustin Richmond; Jeremy Blackstone; Matthew Hogains; Kevin Thai; Ryan Kastner (FCCM, 2016)

Resolve: Generation of High-Performance Sorting Architectures from High-Level Synthesis. - Janarbek Matai; Dustin Richmond; Dajung Lee; Zac Blair; Qiongzhi Wu; Amin Abazari; Ryan Kastner (FPGA, 2016)

A streaming clustering approach using a heterogeneous system for big data analysis. - Dajung Lee; Alric Althoff; Dustin Richmond; Ryan Kastner (ICCAD, 2017)

PynqCopter - An Open-source FPGA Overlay for UAVs. - Brennan Cain; Zain Merchant; Indira Avendano; Dustin Richmond; Ryan Kastner (IEEE BigData, 2018)

Everyone's a Critic: A Tool for Exploring RISC-V Projects. - Dustin Richmond; Michael Barrow; Ryan Kastner (FPL, 2018)

Synthesizable Higher-Order Functions for C++. - Dustin Richmond; Alric Althoff; Ryan Kastner (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Hardware Development for Non-Hardware Engineers. - Dustin Alexander Richmond (2018)

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. - Austin Rovinski; Chun Zhao; Khalid Al-Hawaj; Paul Gao 001; Shaolin Xie; Christopher Torng; Scott Davidson 004; Aporva Amarnath; Luis Vega; Bandhav Veluri; Anuj Rao; Tutu Ajayi; et al. (VLSI Circuits, 2019)

Ruche Networks: Wire-Maximal, No-Fuss NoCs : Special Session Paper. - Dai Cheol Jung; Scott Davidson 004; Chun Zhao; Dustin Richmond; Michael Bedford Taylor (NOCS, 2020)

NoC Symbiosis : (Special Session Paper). - Daniel Petrisko; Chun Zhao; Scott Davidson 004; Paul Gao 001; Dustin Richmond; Michael Bedford Taylor (NOCS, 2020)

ASIC clouds: specializing the datacenter for planet-scale applications. - Michael Bedford Taylor; Luis Vega; Moein Khazraee; Ikuo Magaki; Scott Davidson 004; Dustin Richmond (Commun. ACM, 2020)

Classifying Computations on Multi-Tenant FPGAs. - Mustafa S. Gobulukoglu; Colin Drewes; William Hunter; Ryan Kastner; Dustin Richmond (DAC, 2021)

A Tunable Dual-Edge Time-to-Digital Converter. - Colin Drewes; Steven Harris; Winnie Wang; Richard Appen; Olivia Weng; Ryan Kastner; William Hunter; Christopher McCarty; Dustin Richmond (FCCM, 2021)

Classifying Computations on Multi-Tenant FPGAs. - Mustafa S. Gobulukoglu; Colin Drewes; Bill Hunter; Dustin Richmond; Ryan Kastner (FPGA, 2021)

Taming the Zoo: The Unified GraphIt Compiler Framework for Novel Architectures. - Ajay Brahmakshatriya; Emily Furst; Victor A. Ying; Claire Hsu; Changwan Hong; Max Ruttenberg; Yunming Zhang; Dai Cheol Jung; Dustin Richmond; Michael B. Taylor; Julian Shun; Mark Oskin; et al. (ISCA, 2021)

A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems. - Lin Cheng; Peitian Pan; Zhongyuan Zhao 004; Krithik Ranjan; Jack Weber; Bandhav Veluri; Seyed Borna Ehsani; Max Ruttenberg; Dai Cheol Jung; Preslav Ivanov; Dustin Richmond; Michael B. Taylor; et al. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Beyond Static Parallel Loops: Supporting Dynamic Task Parallelism on Manycore Architectures with Software-Managed Scratchpad Memories. - Lin Cheng; Max Ruttenberg; Dai Cheol Jung; Dustin Richmond; Michael B. Taylor; Mark Oskin; Christopher Batten (ASPLOS (3), 2023)

Turn on, Tune in, Listen up: Maximizing Side-Channel Recovery in Time-to-Digital Converters. - Colin Drewes; Olivia Weng; Keegan Ryan; Bill Hunter; Christopher McCarty; Ryan Kastner; Dustin Richmond (FPGA, 2023)

Pentimento: Data Remanence in Cloud FPGAs. - Colin Drewes; Olivia Weng; Andres Meza 001; Alric Althoff; David Kohlbrenner; Ryan Kastner; Dustin Richmond (ASPLOS (2), 2024)

Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore. - Dai Cheol Jung; Max Ruttenberg; Paul Gao 001; Scott Davidson 004; Daniel Petrisko; Kangli Li; Aditya K. Kamath; Lin Cheng; Shaolin Xie; Peitian Pan; Zhongyuan Zhao 004; Zichao Yue; et al. (ISCA, 2024)

Scalable MatMul-free Language Modeling. - Rui-Jie Zhu 003; Yu Zhang 092; Ethan Sifferman; Tyler Sheaves; Yiqiao Wang 005; Dustin Richmond; Peng Zhou 017; Jason K. Eshraghian (CoRR, 2024)

Turn on, Tune in, and Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters. - Colin Drewes; Tyler Sheaves; Olivia Weng; Keegan Ryan; Bill Hunter; Christopher McCarty; Ryan Kastner; Dustin Richmond (ACM Trans. Reconfigurable Technol. Syst., 2024)