High-performance adaption of ARM processors into Network-on-Chip architectures. - Tung Nguyen; Duy-Hieu Bui; Hai-Phong Phan; Trong-Trinh Dang; Xuan-Tu Tran (SoCC, 2013)

H.264/AVC hardware encoders and low-power features. - Ngoc-Mai Nguyen; Edith Beigné; Suzanne Lesecq; Duy-Hieu Bui; Nam-Khanh Dang; Xuan-Tu Tran (APCCAS, 2014)

Reducing temporal redundancy in MJPEG using Zipfian estimation techniques. - Ngoc-Sinh Nguyen; Duy-Hieu Bui; Xuan-Tu Tran (APCCAS, 2014)

Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications. - Duy-Hieu Bui; Diego Puschini; Simone Bacles-Min; Edith Beigné; Xuan-Tu Tran (ICICDT, 2016)

AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures. - Xuan-Tu Tran; Tung Nguyen; Hai-Phong Phan; Duy-Hieu Bui (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Adaptive Architectures, Circuits and Technology Solutions for Future IoT Systems. - Marc Belleville; Anca Molnos; Gilles Sicard; Jean-Frédéric Christmann; Dominique Morche; Duy-Hieu Bui; Diego Puschini; Suzanne Lesecq; Edith Beigné (J. Low Power Electron., 2017)

AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications. - Duy-Hieu Bui; Diego Puschini; Simone Bacles-Min; Edith Beigné; Xuan-Tu Tran (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization. - Ngo-Doanh Nguyen; Duy-Hieu Bui; Xuan-Tu Tran (APCCAS, 2019)

An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Networks. - Duy-Anh Nguyen; Duy-Hieu Bui; Francesca Iacopi; Xuan-Tu Tran (SoCC, 2019)

A Lightweight AEAD encryption core to secure IoT applications. - Ngo-Doanh Nguyen; Duy-Hieu Bui; Xuan-Tu Tran (APCCAS, 2020)

Reducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Errors in Stationary Blocks. - Xuan-Tu Tran; Ngoc-Sinh Nguyen; Duy-Hieu Bui; Minh-Trien Pham; Hung K. Nguyen; Cong-Kha Pham (EAI Endorsed Trans. Ind. Networks Intell. Syst., 2020)

An Adaptive Hardware Architecture using Quantized HOG Features for Object Detection. - Ngo-Doanh Nguyen; Duy-Hieu Bui; Fawnizu Azmadi Hussin; Xuan-Tu Tran (ICICDT, 2022)

Low-cost Low-Power Implementation of Binary Edwards Curve for Secure Passive RFID Tags. - Hiep Manh Dao; Vincent Beroulle; Yann Kieffer; Xuan-Tu Tran; Duy-Hieu Bui (MCSoC, 2023)

A Hardware Architecture of NIST Lightweight Cryptography Applied in IPSec to Secure High-Throughput Low-Latency IoT Networks. - Sy-Nam Tran; Van-Thuc Hoang; Duy-Hieu Bui (IEEE Access, 2023)

Fully Synthesizable Dynamic Voltage Comparator across technology nodes and scaled supply voltages. - Duy-Hieu Bui; Duc-Manh Tran; Daniele D. Caviglia; Orazio Aiello (ISCAS, 2024)

Exploring 0.3V Inverter Based OTA Designs with NOR3-Based Common Mode Feedback. - Riccardo Della Sala; Orazio Aiello; Ngo-Doanh Nguyen; Duy-Hieu Bui; Xuan-Tu Tran; Giuseppe Scotti (NewCAS, 2025)

SRAM-based Physically Unclonable Function using Lightweight Hamming-Code Fuzzy Extractor for Energy Harvesting Beat Sensors. - Hoang-Long Pham; Duy-Hieu Bui; Xuan-Tu Tran; Orazio Aiello (CoRR, 2025)