An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing. - Ciaran Toal; Dwayne Burns; Kieran McLaughlin; Sakir Sezer; Stephen O'Kane (AHS, 2007)

Novel Content Addressable Memory Architecture for Adaptive Systems. - Xin Yang 010; Sakir Sezer; John V. McCanny; Dwayne Burns (AHS, 2007)

An FPGA Based Memory Efficient Shared Buffer Implementation. - Dwayne Burns; Ciaran Toal; Kieran McLaughlin; Sakir Sezer; Mike Hutton; Kevin Cackovic (FPL, 2007)

Accelerating pattern matching for DPI. - Jun Mu; Sakir Sezer; Gareth Douglas; Dwayne Burns; Emi Garcia; Mike Hutton; Kevin Cackovic (SoCC, 2007)

Programmable CRC circuit architecture. - Ciaran Toal; Sakir Sezer; Xin Yang 010; Kieran McLaughlin; Dwayne Burns; Tiberiu Seceleanu (SoCC, 2007)

A versatile content addressable memory architecture. - Xin Yang 010; Sakir Sezer; John V. McCanny; Dwayne Burns (SoCC, 2007)

DDR3 based lookup circuit for high-performance network processing. - Xin Yang 010; Sakir Sezer; John V. McCanny; Dwayne Burns (SoCC, 2009)

High-Performance random data lookup for network processing. - Xin Yang 010; Sakir Sezer; John V. McCanny; Dwayne Burns (SoCC, 2010)

Transmit and receive filter design for OFDM based WLAN systems. - Pei Xiao 001; Ciaran Toal; Dwayne Burns; Vincent F. Fusco; Colin Cowan (WCSP, 2010)

An Approach for Unifying Rule Based Deep Packet Inspection. - Antonio Muñoz 003; Sakir Sezer; Dwayne Burns; Gareth Douglas (ICC, 2011)

High performance multi-engine regular expression processing. - Thianantha Arumugam; Sakir Sezer; Dwayne Burns; Vishalini Vasu (SoCC, 2011)

Custom purpose regular expression processor architecture for network processing. - Sakir Sezer; Dwayne Burns (ISCAS, 2012)

A 1Gbps FPGA-based wireless baseband MIMO transceiver. - Ciaran Toal; Sakir Sezer; Dwayne Burns; Pei Xiao 001; Vincent F. Fusco (SoCC, 2012)

Fully hardware based WFQ architecture for high-speed QoS packet scheduling. - Kieran McLaughlin; Dwayne Burns; Ciaran Toal; Colm McKillen; Sakir Sezer (Integr., 2012)