A non-uniform sampling ADC architecture with embedded alias-free asynchronous filter. - Dylan Hand; Mike Shuo-Wei Chen (GLOBECOM, 2012)

Performance and Area Optimization of a Bundled-Data Intel Processor through Resynthesis. - Arash Saifhashemi; Dylan Hand; Peter A. Beerel; William Koven; Hong Wang (ASYNC, 2014)

Performance Optimization and Analysis of Blade Designs under Delay Variability. - Dylan Hand; Hsin-Ho Huang; Benmao Cheng; Yang Zhang 014; Matheus Trevisan Moreira; Melvin A. Breuer; Ney Laert Vilar Calazans; Peter A. Beerel (ASYNC, 2015)

Blade - A Timing Violation Resilient Asynchronous Template. - Dylan Hand; Matheus Trevisan Moreira; Hsin-Ho Huang; Danlei Chen; Frederico Butzke; Zhichao Li; Matheus Gibiluka; Melvin A. Breuer; Ney Laert Vilar Calazans; Peter A. Beerel (ASYNC, 2015)

TDTB error detecting latches: Timing violation sensitivity analysis and optimization. - Matheus T. Moreira; Dylan Hand; Peter A. Beerel; Ney Laert Vilar Calazans (ISQED, 2015)

Adding Conditionality to Resilient Bundled-Data Designs. - Dylan Hand; Austin Katrin; William Koven (ASYNC, 2016)

Automatic Retiming of Two-Phase Latch-Based Resilient Circuits. - Huimei Cheng; Hsiao-Lun Wang; Minghe Zhang; Dylan Hand; Peter A. Beerel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)