Feasible Evolutionary and Self-Repairing Hardware by Means of the Dynamic Reconfiguration Capabilities of the FIPSOC Devices. - Juan Manuel Moreno; Jordi Madrenas; Julio Faura; E. Cantó; Joan Cabestany; Josep Maria Insenser (ICES, 1998)

Realization of Self-Repairing and Evolvable Hardware Structures by Means of Implicit Self-Configuration. - Juan Manuel Moreno; Jordi Madrenas; Joan Cabestany; E. Cantó; Rafal Kielbik; Julio Faura; Josep Maria Insenser (Evolvable Hardware, 1999)

A Bipartitioning Algorithm for Dynamic Reconfigurable Programmable Logic. - E. Cantó; Juan Manuel Moreno; Joan Cabestany; Julio Faura; Josep Maria Insenser (FPL, 1999)

The Role of Dynamic Reconfiguration for Implementing Artificial Neural Networks Models in Programmable Hardware. - Juan Manuel Moreno; Joan Cabestany; E. Cantó; Julio Faura; Josep Maria Insenser (IWANN (2), 1999)

Implementation of Virtual Circuits by Means of the FIPSOC Devices. - E. Cantó; Juan Manuel Moreno; Joan Cabestany; Ignacio Lacadena; Josep Maria Insenser (FPL, 2000)

A temporal bipartitioning algorithm for dynamically reconfigurable FPGAs. - E. Cantó; Juan Manuel Moreno; Joan Cabestany; Ignacio Lacadena; Josep Maria Insenser (IEEE Trans. Very Large Scale Integr. Syst., 2001)