Combined Multiplication and Sum-of-Squares Units. - Michael J. Schulte; Louis Marquette; Shankar Krithivasan; E. George Walters III; John Glossner (ASAP, 2003)

Efficient Function Approximation Using Truncated Multipliers and Squarers. - E. George Walters III; Michael J. Schulte (IEEE Symposium on Computer Arithmetic, 2005)

Truncated-matrix multipliers with coefficient shifting. - E. George Walters III; Michael J. Schulte (ACSCC, 2011)

FPGA-accelerated simulation of truncated-matrix multipliers. - E. George Walters III (ACSCC, 2012)

Partial-product generation and addition for multiplication in FPGAs with 6-input LUTs. - E. George Walters III (ACSSC, 2014)

Optimized cubic chebyshev interpolator for elementary function hardware implementations. - Masoud Sadeghian; James E. Stine; E. George Walters III (ISCAS, 2014)

24-bit significand multiplier for FPGA floating-point multiplication. - E. George Walters III (ACSSC, 2015)

Linear and Quadratic Interpolators Using Truncated-Matrix Multipliers and Squarers. - E. George Walters III (Comput., 2015)

Array Multipliers for High Throughput in Xilinx FPGAs with 6-Input LUTs. - E. George Walters III (Comput., 2016)