Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric. - E-Hung Chen; Jihong Ren; Brian S. Leibowitz; Hae-Chang Lee; Qi Lin; Kyung Suk Oh; Frank Lambrecht; Vladimir Stojanovic; Jared Zerbe; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2008)

Edge and Data Adaptive Equalization of Serial-Link Transceivers. - Jackie Koon Lun Wong; E-Hung Chen; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2008)

ADC-Based Serial I/O Receivers. - E-Hung Chen; Chih-Kong Ken Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links. - Jaeha Kim; E-Hung Chen; Jihong Ren; Brian S. Leibowitz; Patrick Satarzadeh; Jared Zerbe; Chih-Kong Ken Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding. - Tamer A. Ali 001; Won Ho Park; Preeti Mulage; E-Hung Chen; Ron Ho; Chih-Kong Ken Yang (VLSIC, 2012)

Power Optimized ADC-Based Serial Link Receiver. - E-Hung Chen; Ramy Yousry; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2012)

A digitally-calibrated 10GS/s reconfigurable flash ADC in 65-nm CMOS. - Ramy Yousry; Henry Park; E-Hung Chen; Chih-Kong Ken Yang (ISCAS, 2013)

A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm. - Seuk Son; Hanseok Kim; Myeong-Jae Park; Kyung-Hoon Kim; E-Hung Chen; Brian S. Leibowitz; Jaeha Kim (IEEE J. Solid State Circuits, 2013)

A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering. - Masum Hossain; E-Hung Chen; Reza Navid; Brian S. Leibowitz; Chuen-Huei Adam Chou; Simon Li; Myeong-Jae Park; Jihong Ren; Barry Daly; Bruce Su; Makarand Shirasgaonkar; Fred Heaton; et al. (VLSIC, 2014)

A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology. - Reza Navid; E-Hung Chen; Masum Hossain; Brian S. Leibowitz; Jihong Ren; Chuen-Huei Adam Chou; Barry Daly; Marko Aleksic; Bruce Su; Simon Li; Makarand Shirasgaonkar; Fred Heaton; et al. (IEEE J. Solid State Circuits, 2015)