High-Speed Virtual Logic Network on Chip Router Architecture for Various Topologies. - E. Lakshmi Prasad; M. N. Giri Prasad; A. R. Reddy (Comput. Electr. Eng., 2018)

Secure Scan Architecture for Enhanced Testability and Resistance Against Side-Channel Attacks in Cryptographic ICs. - A. Swetha Priya; S. Kamatchi; E. Lakshmi Prasad (IEEE Access, 2025)