Advanced TCAD for predictive FinFETs Vth mismatch using full 3D process/device simulation. - E. M. Bazizi; Alban Zaka; Tom Herrmann; Francis Benistant; J. H. M. Tin; J. P. Goh; L. Jiang; M. Joshi; H. van Meer; K. Korablev (ESSDERC, 2014)

Highly-Doped Through-Contact Silicon Epi Design at 3 nm node. - Sushant Mittal; Ashish Pal; Mehdi Saremi; J. Ferrell; M. Haverty; T. Miyashita; N. Kim; El Mehdi Bazizi; Blessy Alexander; A. B. Sachid; Buvna Ayyagari (DRC, 2019)

Low-Frequency Noise Reduction in 22FDX®: Impact of Device Geometry and Back Bias. - Luca Pirro; Alban Zaka; Olaf Zimmerhackl; T. Hermann; Michael Otto 003; E. M. Bazizi; Jan Hoentschel; X. Li; R. Taylor (IRPS, 2019)

TCAD Simulation on FinFET n-type Power Device HCI Reliability Improvement. - Benyuan Zhu; E. M. Bazizi; J. H. M. Tng; Z. Li; E. K. Banghart; M. K. Hassan; Y. Hu; D. Zhou; D. Choi; L. Qin; Xuan Wan (IRPS, 2019)

Modeling and Optimization of Advanced 3D NAND Memory. - Mehdi Saremi; Ashish Pal; Liu Jiang; El Mehdi Bazizi; Helen Lee; Xi-Wei Lin; Blessy Alexander; Buvna Ayyagari-Sangamalli (DRC, 2020)

Integration scheme for 3D NAND with nonreplacement word line and its cell characteristics investigation. - Liu Jiang; Chang Seok Kang; Ashish Pal; El Mehdi Bazizi; Tomohiko Kitajima; Nancy Fung; Gabriela Alva; Amy Child; Bhaskar Bhuyan; Takehito Koshizawa; Sung-Kwan Kang; Gill Lee; et al. (IMW, 2021)

Contact Cavity Shaping and Selective SiGe: B Low-Temperature Epitaxy Process Solution for sub 10-9 Ω.cm2 Contact Resistivity in Nonplanar FETs. - N. Breil; B.-C. Lee; J. Avila Avendano; J. Jewell; M. Vellaikal; E. Newman; E. M. Bazizi; Ashish Pal; L. Liu; Oleg Gluschenkov; A. Greene; S. Mochizuki; et al. (VLSI Technology and Circuits, 2023)

BEOL Interconnect Innovation: Materials, Process and Systems Co-optimization for 3nm Node and Beyond. - Gaurav Thareja; Ashish Pal; Xingye Wang; Sefa Dag; Shi You; Shashank Sharma; Qing Zhu; Carmen L. Cervantes; Shinjae Hwang; Matthew Spuller; Ben Ng; Pradeep S. Kumar; et al. (VLSI Technology and Circuits, 2023)

D2W Hybrid Bonding Challenges for HBM. - Gaurav Mehta; Jonathan Abdilla; Raymond Hung; El Mehdi Bazizi; Yong Chang Bum; Djuro Bikajlevic; Liu Jiang; Gregory Costrini (IMW, 2024)

Gate-All-Around SRAM: Performance Investigation and Optimization Towards Vccmin Scaling. - Pratik B. Vyas; Ashish Pal; Gregory Costrini; Benjamin Colombeau; Bala Haran; Subi Kengeri; El Mehdi Bazizi (IMW, 2024)

Modeling of Negative Bias Temperature Instability (NBTI) for Gate-All-Around (GAA) Stacked Nanosheet Technology. - Leitao Liu; Jingtian Fang; Ashish Pal; Plamen Asenov; Mohit Bajaj; Bei Deng; Xi-Wei Lin; Souvik Mahapatra; Subi Kengeri; El Mehdi Bazizi (IRPS, 2024)

Material, Process and System Level Analysis for Parasitic Reduction of Next Generation Logic Technology in Conjunction with Backside Power Delivery. - Ashish Pal; Sefa Dag; Pratik B. Vyas; Gregory Costrini; Vinod Reddy; Veeraraghavan Basker; Allen Yeong; Benjamin Colombeau; Bala Haran; Subi Kengeri; El Mehdi Bazizi (VLSI Technology and Circuits, 2024)

Novel Material, Process and Device Innovations for Next Generation Silicon Carbide (SiC) Trench MOSFET Technology. - Pratik B. Vyas; Ludovico Megalini; Ashish Pal; Joshua Holt; Archana Kumar; Stephen Weeks; Charisse Zhao; Lucien Date; Hansel Lo; Michel Khoury; Safdar Muhammad; Fabian Piallat; et al. (VLSI Technology and Circuits, 2024)