The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and Beyond. - E. Ray Hsieh; C. W. Chang; C. C. Chuang; H. W. Chen; Steve S. Chung (VLSI Circuits, 2019)

A Pulsed RTN Transient Measurement Technique: Demonstration on the Understanding of the Switching in Resistance Memory. - E. Ray Hsieh; H. W. Cheng; Z. H. Huang; C. H. Chuang; S. P. Yang; Steve S. Chung (IRPS, 2020)

A Reliable Triple-Level Operation of Resistive-Gate Flash Featuring Forming-Free and High Immunity to Sneak Path. - W. Y. Yang; E. Ray Hsieh; C. H. Cheng; B. Y. Chen; K. S. Li; Steve S. Chung (IRPS, 2021)

NVDimm-FE: A High-density 3D Architecture of 3-bit/c 2TnCFE to Break Great Memory Wall with 10 ns of PGM-pulse, 1010 Cycles of Endurance, and Decade Lifetime at 103 °C. - E. Ray Hsieh; J. K. Chang; T. Y. Tang; Y. J. Li; C. W. Liang; M. Y. Lin; S. Y. Huang; C. J. Su; J. C. Guo; Steve S. Chung (VLSI Technology and Circuits, 2022)

3-bits-per-cell 2T32CFE nvTCAM by Angstrom-laminated Ferroelectric Layers with 10¹¹ Cycles of Endurance and 4.92V of Ultra-wide Memory-windows for In-memory-searching. - E. Ray Hsieh; Ying-Tsan Tang; Cheng-Rui Liu; Sheng-Min Wang; Y. L. Hsueh; R. Q. Lin; Yi Xiang Huang; Yu-Ting Chen (VLSI Technology and Circuits, 2023)

µPUA-Net: PowerMLP Model Size Shrinking Method with Accuracy Maintaining. - Yu-Shan Chou; You-Jin Liu; Kai-Lun Pien; Tong-Hou Cheong; Chieh-Chen Yu; Ying-Hui Cheng; Yu-Hsuan Chiang; E. Ray Hsieh; Chien-Chang Chen (BraTS-Lighthouse/AIMS-TBI@MICCAI (1), 2025)

A Logic-Compatible 2-Transistor Embedded Bipolar RRAM MACRO: A 28-nm Multiple-Time Programmable (MTP) Memory Without Extra Masks. - Yi Xiang Huang; Y. S. Lin; P. S. Huang; E. Ray Hsieh (IEEE Solid State Circuits Lett., 2026)