Applications of the inner product computer. - Earl E. Swartzlander Jr. (ACM Annual Conference, 1973)

The Quasi-Serial Multiplier. - Earl E. Swartzlander Jr. (IEEE Trans. Computers, 1973)

Parallel Counters. - Earl E. Swartzlander Jr. (IEEE Trans. Computers, 1973)

The inner product computer (Ph.D. Thesis abstr.). - Earl E. Swartzlander Jr. (IEEE Trans. Inf. Theory, 1973)

Review of "Introduction to Mathematical Techniques in Pattern Recognition" by Harry C. Andrews. - Earl E. Swartzlander Jr. (IEEE Trans. Syst. Man Cybern., 1973)

Review of "Fundamentals of Pattern Recognition" by Edward A. Patrick. - Earl E. Swartzlander Jr. (IEEE Trans. Syst. Man Cybern., 1973)

The Sign/Logarithm Number System. - Earl E. Swartzlander Jr.; Aristides G. Alexopoulos (IEEE Trans. Computers, 1975)

Microprogrammed control for signal processing. - Earl E. Swartzlander Jr. (MICRO, 1977)

Merged arithmetic for signal processing. - Earl E. Swartzlander Jr. (IEEE Symposium on Computer Arithmetic, 1978)

Inner Product Computers. - Earl E. Swartzlander Jr.; Barry K. Gilbert; Irving S. Reed (IEEE Trans. Computers, 1978)

Microprogrammed Control for Specialized Processors. - Earl E. Swartzlander Jr. (IEEE Trans. Computers, 1979)

Comment on "The Focus Number System". - Earl E. Swartzlander Jr. (IEEE Trans. Computers, 1979)

A Routing Algorithm for Signal Processing Networks. - Earl E. Swartzlander Jr.; Douglas J. Heath (IEEE Trans. Computers, 1979)

Signal processing architectures with VLSI. - Earl E. Swartzlander Jr. (ICASSP, 1980)

Merged Arithmetic. - Earl E. Swartzlander Jr. (IEEE Trans. Computers, 1980)

Arithmetic for Ultra-High-Speed Tomography. - Earl E. Swartzlander Jr.; Barry K. Gilbert (IEEE Trans. Computers, 1980)

Supersystems: Technology and Architecture. - Earl E. Swartzlander Jr.; Barry K. Gilbert (IEEE Trans. Computers, 1982)

Digital signal processing with VLSI technology. - Earl E. Swartzlander Jr.; Louis S. Lome; George Hallnor (ICASSP, 1983)

Sign/Logarithm Arithmetic for FFT Implementation. - Earl E. Swartzlander Jr.; D. V. Satish Chandra; H. Troy Nagle Jr.; Scott A. Starks (IEEE Trans. Computers, 1983)

Fast transform processor implementation. - Earl E. Swartzlander Jr.; George Hallnor (ICASSP, 1984)

Arithmetic for high speed FFT implementation. - Earl E. Swartzlander Jr.; John A. Eldon (IEEE Symposium on Computer Arithmetic, 1985)

VLSI Testing: A Decade of Experience. - Earl E. Swartzlander Jr.; John A. Eldon; De D. Hsu (COMPCON, 1985)

Image processing address generator chip. - John A. Eldon; Zoltan Stroll; Earl E. Swartzlander Jr. (ICASSP, 1985)

Foreword: Advances in Distributed Computing Systems. - Stephen F. Lundstrom; Earl E. Swartzlander Jr. (IEEE Trans. Software Eng., 1985)

Generic signal processor implementation with VHSIC. - Earl E. Swartzlander Jr. (J. VLSI Signal Process., 1990)

The redundant cell adder. - Thomas W. Lynch; Earl E. Swartzlander Jr. (IEEE Symposium on Computer Arithmetic, 1991)

High-speed multiplier design using multi-input counter and compressor circuits. - Mayur Mehta; Vijay Parmar; Earl E. Swartzlander Jr. (IEEE Symposium on Computer Arithmetic, 1991)

Arithmetic for digital neural networks. - David Zhang 001; Graham A. Jullien; William C. Miller; Earl E. Swartzlander Jr. (IEEE Symposium on Computer Arithmetic, 1991)

The case for application specific computing. - Earl E. Swartzlander Jr. (ASAP, 1991)

Advanced technology for improved signal processor efficiency. - Earl E. Swartzlander Jr. (ASAP, 1992)

Arithmetic Error Analysis of a new Reciprocal Cell. - Vijay K. Jain; Gibert E. Perez; Earl E. Swartzlander Jr. (ICCD, 1992)

Modified Booth Algorithm for High Radix Multiplication. - Philip E. Madrid; Brian Millar; Earl E. Swartzlander Jr. (ICCD, 1992)

Implementation of Parallel Processors with Wafer Scale Integration. - Thomas K. Callaway; Earl E. Swartzlander Jr. (IPPS, 1992)

Wafer-Scale Integration: Architectures and Algorithms - Guest Editors' Introduction. - W. Kent Fuchs; Earl E. Swartzlander Jr. (Computer, 1992)

A Spanning Tree Carry Lookahead Adder. - Thomas W. Lynch; Earl E. Swartzlander Jr. (IEEE Trans. Computers, 1992)

A radix-8 wafer scale FFT processor. - Earl E. Swartzlander Jr.; Vijay K. Jain; Hiroomi Hikawa (J. VLSI Signal Process., 1992)

Estimating the power consumption of CMOS adders. - Thomas K. Callaway; Earl E. Swartzlander Jr. (IEEE Symposium on Computer Arithmetic, 1993)

Exact rounding of certain elementary functions. - Michael J. Schulte; Earl E. Swartzlander Jr. (IEEE Symposium on Computer Arithmetic, 1993)

Reduced area multipliers. - K'Andrea C. Bickerstaff; Michael J. Schulte; Earl E. Swartzlander Jr. (ASAP, 1993)

VLSI Concurrent Error Correcting Adders and Multipliers. - Yuang-Ming Hsu; Earl E. Swartzlander Jr. (DFT, 1993)

A Comparative Evaluation of Adders Based on Performance and Testability. - Rathish Jayabharathi; Thomas Thomas; Earl E. Swartzlander Jr. (ICCD, 1993)

Superpipelined Adder Designs. - Ishaq H. Unwala; Earl E. Swartzlander Jr. (ISCAS, 1993)

Design and implementation of an interface control unit for rapid prototyping. - Mohammad S. Khan; Earl E. Swartzlander Jr. (RSP, 1993)

Modified Booth algorithm for high radix fixed-point multiplication. - Philip E. Madrid; Brian Millar; Earl E. Swartzlander Jr. (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Overlapped Subarray Segmentation: An Efficient Test Method for Cellular Arrays. - Earl E. Swartzlander Jr.; Miroslaw Malek (VLSI Design, 1993)

A systolic array for 2-D DFT and 2-D DCT. - Hyesook Lim; Earl E. Swartzlander Jr. (ASAP, 1994)

A variable-precision interval arithmetic processor. - Michael J. Schulte; Earl E. Swartzlander Jr. (ASAP, 1994)

Reliability Estimation for Time Redundant Error Correcting Adders and Multipliers. - Yuang-Ming Hsu; Earl E. Swartzlander Jr. (DFT, 1994)

A New Asynchronous Multiplier Using Enable/Disable CMOS Differential Logic. - Edwin de Angel; Earl E. Swartzlander Jr.; Jacob A. Abraham (ICCD, 1994)

What Types of Research Papers Should We Be Writing? - Thomas L. Casavant; Chi-Yuan Chin; Wen-Tsuen Chen; Kang G. Shin; Earl E. Swartzlander Jr.; Joseph E. Urban (ICPADS, 1994)

Is It Possible to Fairly Compare Interconnection Networks?. - José Duato; C. T. Howard Ho; Ferng-Ching Lin; Lionel M. Ni; Earl E. Swartzlander Jr. (ICPADS, 1994)

Sorting Networks with Built-In Error Correction. - Yuang-Ming Hsu; Earl E. Swartzlander Jr. (ICPADS, 1994)

Heterogeneous Parallel Computing. - Earl E. Swartzlander Jr. (ICPADS, 1994)

A Standardized Interface Control Unit for Heterogeneous Digital Signal Processors. - Mohammad S. Khan; Earl E. Swartzlander Jr. (ISCAS, 1994)

Optimal initial approximations for the Newton-Raphson division algorithm. - Michael J. Schulte; J. Omar; Earl E. Swartzlander Jr. (Computing, 1994)

Boundary scan in board manufacturing. - Thomas A. Ziaja; Earl E. Swartzlander Jr. (J. Electron. Test., 1994)

Hardware Designs for Exactly Rounded Elemantary Functions. - Michael J. Schulte; Earl E. Swartzlander Jr. (IEEE Trans. Computers, 1994)

Fast multiplier bit-product matrix reduction using bit-ordering and parity generation. - Ben C. Drerup; Earl E. Swartzlander Jr. (J. VLSI Signal Process., 1994)

Parallel counter implementation. - Robert F. Jones; Earl E. Swartzlander Jr. (J. VLSI Signal Process., 1994)

Editorial. - Earl E. Swartzlander Jr. (J. VLSI Signal Process., 1994)

Cascaded Implementation of an Iterative Inverse–Square–Root Algorithm, with Overflow Lookahead. - Hercule Kwan; Robert Leonard Nelson Jr.; Earl E. Swartzlander Jr. (IEEE Symposium on Computer Arithmetic, 1995)

Hardware Design and Arithmetic Algorithms for a Variable-Precision, Interval Arithmetic Coprocessor. - Michael J. Schulte; Earl E. Swartzlander Jr. (IEEE Symposium on Computer Arithmetic, 1995)

Recomputing by Operand Exchanging: A Time-redundancy Approach for Fault-tolerant Neural Networks. - Yuang-Ming Hsu; Earl E. Swartzlander Jr.; Vincenzo Piuri (ASAP, 1995)

A Processor for Staggered Interval Arithmetic. - Michael J. Schulte; Earl E. Swartzlander Jr. (ASAP, 1995)

Efficient time redundancy for error correcting inner-product units and convolvers. - Yuang-Ming Hsu; Vincenzo Piuri; Earl E. Swartzlander Jr. (DFT, 1995)

Characterization and analysis of errors in circuit test. - Thomas A. Ziaja; Earl E. Swartzlander Jr. (DFT, 1995)

An efficient systolic array for the discrete cosine transform based on prime-factor decomposition . - Hyesook Lim; Earl E. Swartzlander Jr. (ICCD, 1995)

A coprocessor for accurate and reliable numerical computations. - Michael J. Schulte; Earl E. Swartzlander Jr. (ICCD, 1995)

Time-Redundant Multiple Computation for Fault-Tolerant Digital Neural Networks. - Yuang-Ming Hsu; Vincenzo Piuri; Earl E. Swartzlander Jr. (ISCAS, 1995)

Fault-Tolerant Neural Architectures: The Use of Rotated Operands. - Yuang-Ming Hsu; Vincenzo Piuri; Earl E. Swartzlander Jr. (ISCAS, 1995)

Merged CORDIC Algorithm. - Shaoyun Wang; Earl E. Swartzlander Jr. (ISCAS, 1995)

Rapid prototyping fault-tolerant heterogeneous digital signal processing systems. - Mohammad S. Khan; Earl E. Swartzlander Jr. (RSP, 1995)

A software interface and hardware design for variable-precision interval arithmetic. - Michael J. Schulte; Earl E. Swartzlander Jr. (Reliab. Comput., 1995)

Parallel reduced area multipliers. - K'Andrea C. Bickerstaff; Michael J. Schulte; Earl E. Swartzlander Jr. (J. VLSI Signal Process., 1995)

Finite Word-Length Effects Of An Unified Systolic Array For 2-D DCT/IDCT. - Hyesook Lim; Changhoon Yim; Earl E. Swartzlander Jr. (ASAP, 1996)

Fault tolerant Newton-Raphson dividers using time shared TMR. - W. Lynn Gallagher; Earl E. Swartzlander Jr. (DFT, 1996)

Comprehensive Modeling of VLSI Test. - Thomas A. Ziaja; Earl E. Swartzlander Jr. (DFT, 1996)

Multidimensional systolic arrays for multidimensional DFTs. - Hyesook Lim; Earl E. Swartzlander Jr. (ICASSP, 1996)

Granularly-pipelined CORDIC processors for sine and cosine generators. - Shaoyun Wang; Vincenzo Piuri; Earl E. Swartzlander Jr. (ICASSP, 1996)

Calculators. - Earl E. Swartzlander Jr. (IEEE Ann. Hist. Comput., 1996)

Variable-precision, interval arithmetic coprocessors. - Michael J. Schulte; Earl E. Swartzlander Jr. (Reliab. Comput., 1996)

A new design for a lookahead carry generator. - Hercule Kwan; Robert Leonard Nelson Jr.; Earl E. Swartzlander Jr. (J. VLSI Signal Process., 1996)

High-Speed Computer Arithmetic. - Earl E. Swartzlander Jr. (The Computer Science and Engineering Handbook, 1997)

Power-Delay Characteristics of CMOS Multipliers. - Thomas K. Callaway; Earl E. Swartzlander Jr. (IEEE Symposium on Computer Arithmetic, 1997)

Realization of a nonlinear digital filter on a DSP array processor. - Hercule Kwan; Edward J. Powers; Earl E. Swartzlander Jr. (ASAP, 1997)

Fast Error-Correcting Newton-Raphson Dividers Using Time Shared TMR. - W. Lynn Gallagher; Earl E. Swartzlander Jr. (DFT, 1997)

Survey of low power techniques for ROMs. - Edwin de Angel; Earl E. Swartzlander Jr. (ISLPED, 1997)

Hybrid CORDIC Algorithms. - Shaoyun Wang; Vincenzo Piuri; Earl E. Swartzlander Jr. (IEEE Trans. Computers, 1997)

Error-Correcting Goldschmidt Dividers Using Time Shared TMR. - W. Lynn Gallagher; Earl E. Swartzlander Jr. (DFT, 1998)

Merged Arithmetic for Computing Wavelet Transforms. - Gwangwoo Choe; Earl E. Swartzlander Jr. (Great Lakes Symposium on VLSI, 1998)

A reduction scheme to optimize the Wallace multiplier. - Moises E. Robinson; Earl E. Swartzlander Jr. (ICCD, 1998)

VLSI, MCM, and WSI: A Design Comparison. - Earl E. Swartzlander Jr. (IEEE Des. Test Comput., 1998)

Editorial Message. - Mary Jane Irwin; Sun-Yuan Kung; Earl E. Swartzlander Jr. (J. VLSI Signal Process., 1998)

Power Consumption in Fast Dividers Using Time Shared TMR. - W. Lynn Gallagher; Earl E. Swartzlander Jr. (DFT, 1999)

Time-Shared Modular Redundancy for Fault-Tolerant FFT Processors. - Vincenzo Piuri; Earl E. Swartzlander Jr. (DFT, 1999)

High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection. - Jae Hun Choi; Jae-Hyuck Kwak; Earl E. Swartzlander Jr. (ICCD, 1999)

Bipolar merged arithmetic for wavelet architectures. - Gwangwoo Choe; Earl E. Swartzlander Jr. (ISCAS (3), 1999)

Parallel Implementation of Multidimensional Transforms without Interprocessor Communication. - Francescomaria Marino; Earl E. Swartzlander Jr. (IEEE Trans. Computers, 1999)

Multidimensional systolic arrays for the implementation of discrete Fourier transforms. - Hyesook Lim; Earl E. Swartzlander Jr. (IEEE Trans. Signal Process., 1999)

A parallel implementation of the 2-D discrete wavelet transform without interprocessor communications. - Francescomaria Marino; Vincenzo Piuri; Earl E. Swartzlander Jr. (IEEE Trans. Signal Process., 1999)

A 16-Bit x 16-Bit MAC Design Using Fast 5: 2 Compressors. - Ohsang Kwon; Earl E. Swartzlander Jr.; Kevin J. Nowka (ASAP, 2000)

Fault-Tolerant High-Performance Cordic Processors. - Jae-Hyuck Kwak; Earl E. Swartzlander Jr.; Vincenzo Piuri (DFT, 2000)

Fault-Tolerant Newton-Raphson and Goldschmidt Dividers Using Time Shared TMR. - W. Lynn Gallagher; Earl E. Swartzlander Jr. (IEEE Trans. Computers, 2000)

A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms. - Hyesook Lim; Vincenzo Piuri; Earl E. Swartzlander Jr. (IEEE Trans. Computers, 2000)

A Family of Variable-Precision Interval Arithmetic Processors. - Michael J. Schulte; Earl E. Swartzlander Jr. (IEEE Trans. Computers, 2000)

High-Speed CORDIC Based on an Overlapped Architecture and a Novel sigma-Prediction Method. - Jae-Hyuck Kwak; Jae Hun Choi; Earl E. Swartzlander Jr. (J. VLSI Signal Process., 2000)

Analysis of Column Compression Multipliers. - K'Andrea C. Bickerstaff; Earl E. Swartzlander Jr.; Michael J. Schulte (IEEE Symposium on Computer Arithmetic, 2001)

Enhanced Concurrent Error Correcting Arithmetic Unit Design Using Alternating Logic. - Tat Ngai; Earl E. Swartzlander Jr.; Chen He (DFT, 2001)

A fast hybrid carry-lookahead/carry-select adder design. - Ohsang Kwon; Earl E. Swartzlander Jr.; Kevin J. Nowka (ACM Great Lakes Symposium on VLSI, 2001)

Time-shared TMR for fault-tolerant CORDIC processors. - Jae-Hyuck Kwak; Vincenzo Piuri; Earl E. Swartzlander Jr. (ICASSP, 2001)

DCT Implementation with Distributed Arithmetic. - Sungwook Yu; Earl E. Swartzlander Jr. (IEEE Trans. Computers, 2001)

A pipelined architecture for the multidimensional DFT. - Sungwook Yu; Earl E. Swartzlander Jr. (IEEE Trans. Signal Process., 2001)

Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOS. - Steven M. Currie; Paul R. Schumacher; Barry K. Gilbert; Earl E. Swartzlander Jr.; Barbara A. Randall (ASAP, 2002)

An Analysis of the CORDIC Algorithm for Direct Digital Frequency Synthesis. - Chang Yong Kang; Earl E. Swartzlander Jr. (ASAP, 2002)

A scaled DCT architecture with the CORDIC algorithm. - Sungwook Yu; Earl E. Swartzlander Jr. (IEEE Trans. Signal Process., 2002)

A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells. - Ohsang Kwon; Kevin J. Nowka; Earl E. Swartzlander Jr. (J. VLSI Signal Process., 2002)

An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform. - Ayman M. El-Khashab; Earl E. Swartzlander Jr. (ASAP, 2003)

Quadruple Time Redundancy Adders. - Whitney J. Townsend; Jacob A. Abraham; Earl E. Swartzlander Jr. (DFT, 2003)

A self-testing method for the pipelined A/D converter. - Jaeki Yoo; Edward Lee; Earl E. Swartzlander Jr. (ISCAS (1), 2003)

Guest Editorial. - Mohammad Ibrahim; Earl E. Swartzlander Jr. (J. VLSI Signal Process., 2003)

Parallel Montgomery Multipliers. - Moboluwaji O. Sanu; Earl E. Swartzlander Jr.; Craig M. Chase (ASAP, 2004)

A Review of Large Parallel Counter Designs. - Earl E. Swartzlander Jr. (ISVLSI, 2004)

Parallel Prefix Adder Design with Matrix Representation. - Youngmoon Choi; Earl E. Swartzlander Jr. (IEEE Symposium on Computer Arithmetic, 2005)

Multiply-Accumulate Architecture for a Special Class of Optimal Extension Fields. - Moboluwaji O. Sanu; Earl E. Swartzlander Jr. (ASAP, 2005)

Three Dimensional System on Chip Technology, invited. - Earl E. Swartzlander Jr. (IWSOC, 2005)

Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology. - Tung N. Pham; Earl E. Swartzlander Jr. (ASAP, 2006)

Systolic FFT Processors: Past, Present and Future. - Earl E. Swartzlander Jr. (ASAP, 2006)

Digit-pipelined direct digital frequency synthesis based on differential CORDIC. - Chang Yong Kang; Earl E. Swartzlander Jr. (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Serial Parallel Multiplier Design in Quantum-dot Cellular Automata. - Heumpil Cho; Earl E. Swartzlander Jr. (IEEE Symposium on Computer Arithmetic, 2007)

Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine. - Hani H. Saleh; Bassam Jamil Mohd; Adnan Aziz; Earl E. Swartzlander Jr. (ICCD, 2007)

The hazard-free superscalar pipeline fast fourier transform algorithm and architecture. - Bassam Jamil Mohd; Adnan Aziz; Earl E. Swartzlander Jr. (VLSI-SoC, 2007)

The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm. - Bassam Jamil Mohd; Earl E. Swartzlander Jr.; Adnan Aziz (VLSI-SoC (Selected Papers), 2007)

The Negative Two's Complement Number System. - Earl E. Swartzlander Jr. (J. VLSI Signal Process., 2007)

A rounding method with improved error tolerance for division by convergence. - Inwook Kong; Earl E. Swartzlander Jr. (ACSCC, 2008)

Fused floating-point arithmetic for DSP. - Earl E. Swartzlander Jr.; Hani H. Saleh (ACSCC, 2008)

32 bit single cycle nonlinear VLSI cell for the ICA algorithm. - Vijay K. Jain; Earl E. Swartzlander Jr. (ICASSP, 2008)

A floating-point fused dot-product unit. - Hani H. Saleh; Earl E. Swartzlander Jr. (ICCD, 2008)

High performance IP lookup circuit using DDR SDRAM. - Xin Yang 010; Jun Mu; Sakir Sezer; John V. McCanny; Earl E. Swartzlander Jr. (SoCC, 2008)

Speculative Carry Generation With Prefix Adder. - Youngmoon Choi; Earl E. Swartzlander Jr. (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Bridge Floating-Point Fused Multiply-Add Design. - Eric Quinnell; Earl E. Swartzlander Jr.; Carl Lemonds (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Negative Save Sign Extension for Multi-term Adders and Multipliers. - Robert T. Grisamore; Earl E. Swartzlander Jr. (J. Signal Process. Syst., 2008)

Systolic FFT Processors: A Personal Perspective. - Earl E. Swartzlander Jr. (J. Signal Process. Syst., 2008)

Floating-Point Computer Arithmetic. - Eric Quinnell; Earl E. Swartzlander Jr. (Wiley Encyclopedia of Computer Science and Engineering, 2008)

Fixed-Point Computer Arithmetic. - Earl E. Swartzlander Jr. (Wiley Encyclopedia of Computer Science and Engineering, 2008)

A Power-Scalable Switch-Based Multi-processor FFT. - Bassam Jamil Mohd; Earl E. Swartzlander Jr. (ASAP, 2009)

Design of a Goldschmidt iterative divider for quantum-dot cellular automata. - Inwook Kong; Earl E. Swartzlander Jr.; Seong-Wan Kim (NANOARCH, 2009)

JavaFlow - A Java dataflow machine. - Robert J. Ascott; Earl E. Swartzlander Jr. (SoCC, 2009)

ASIC evaluation of ECHO hash function. - Liang Lu; Máire O'Neill; Earl E. Swartzlander Jr. (SoCC, 2009)

Adder and Multiplier Design in Quantum-Dot Cellular Automata. - Heumpil Cho; Earl E. Swartzlander Jr. (IEEE Trans. Computers, 2009)

A novel technique for tunable mismatch shaping in oversampled digital-to-analog converters. - Waqas Akram; Earl E. Swartzlander Jr. (ICASSP, 2010)

QCA Systolic Matrix Multiplier. - Liang Lu; Weiqiang Liu 001; Máire O'Neill; Earl E. Swartzlander Jr. (ISVLSI, 2010)

High speed recursion-free CORDIC architecture. - Shakeel S. Abdulla; Haewoon Nam; Earl E. Swartzlander Jr.; Jacob A. Abraham (SoCC, 2010)

A Rounding Method to Reduce the Required Multiplier Precision for Goldschmidt Division. - Inwook Kong; Earl E. Swartzlander Jr. (IEEE Trans. Computers, 2010)

Priority Tries for IP Address Lookup. - Hyesook Lim; Changhoon Yim; Earl E. Swartzlander Jr. (IEEE Trans. Computers, 2010)

Adaptive CORDIC: Using Parallel Angle Recoding to Accelerate Rotations. - Terence K. Rodrigues; Earl E. Swartzlander Jr. (IEEE Trans. Computers, 2010)

A Reduced Complexity Wallace Multiplier Reduction. - Ron S. Waters; Earl E. Swartzlander Jr. (IEEE Trans. Computers, 2010)

A floating-point fused FFT butterfly arithmetic unit with Merged Multiple-Constant Multipliers. - Jae Hong Min; Seong-Wan Kim; Earl E. Swartzlander Jr. (ACSCC, 2011)

The fully-serial pipelined multiplier. - Andrew G. Shafer; Lyndsi R. Parker; Earl E. Swartzlander Jr. (ACSCC, 2011)

Hybrid residue generators for increased efficiency. - Michael B. Sullivan 001; Earl E. Swartzlander Jr. (ACSCC, 2011)

Design rules for Quantum-dot Cellular Automata. - Weiqiang Liu 001; Liang Lu; Máire O'Neill; Earl E. Swartzlander Jr. (ISCAS, 2011)

Quantifying academic placer performance on custom designs. - Samuel I. Ward; David A. Papa; Zhuo Li 001; Cliff N. Sze; Charles J. Alpert; Earl E. Swartzlander Jr. (ISPD, 2011)

A Goldschmidt Division Method With Faster Than Quadratic Convergence. - Inwook Kong; Earl E. Swartzlander Jr. (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Tunable Mismatch Shaping for Quadrature Bandpass Delta-Sigma Data Converters. - Waqas Akram; Earl E. Swartzlander Jr. (J. Signal Process. Syst., 2011)

Modified non-restoring division algorithm with improved delay profile and error correction. - Kihwan Jun; Earl E. Swartzlander Jr. (ACSCC, 2012)

A review of QCA adders and metrics. - Weiqiang Liu 001; Máire O'Neill; Earl E. Swartzlander Jr. (ACSCC, 2012)

A low-power dual-path floating-point fused add-subtract unit. - Jae Hong Min; Jongwook Sohn; Earl E. Swartzlander Jr. (ACSCC, 2012)

Truncated error correction for flexible approximate multiplication. - Michael B. Sullivan 001; Earl E. Swartzlander Jr. (ACSCC, 2012)

Long Residue Checking for Adders. - Michael B. Sullivan 001; Earl E. Swartzlander Jr. (ASAP, 2012)

Cost-efficient decimal adder design in Quantum-dot cellular automata. - Weiqiang Liu 001; Liang Lu; Máire O'Neill; Earl E. Swartzlander Jr. (ISCAS, 2012)

Keep it straight: teaching placement how to better handle designs with datapaths. - Samuel I. Ward; Myung-Chul Kim; Natarajan Viswanathan; Zhuo Li 001; Charles J. Alpert; Earl E. Swartzlander Jr.; David Z. Pan (ISPD, 2012)

Hybrid Han-Carlson adder. - Sreenivaas Muthyala Sudhakar; Kumar P. Chidambaram; Earl E. Swartzlander Jr. (MWSCAS, 2012)

A new hierarchical packet classification algorithm. - Hyesook Lim; Soohyun Lee; Earl E. Swartzlander Jr. (Comput. Networks, 2012)

FFT Implementation with Fused Floating-Point Operations. - Earl E. Swartzlander Jr.; Hani H. Saleh (IEEE Trans. Computers, 2012)

Improved Architectures for a Fused Floating-Point Add-Subtract Unit. - Jongwook Sohn; Earl E. Swartzlander Jr. (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Implementation of a high speed multiplier using carry lookahead adders. - Wesley Chu; Ali I. Unwala; Pohan Wu; Earl E. Swartzlander Jr. (ACSSC, 2013)

On separable error detection for addition. - Michael B. Sullivan 001; Earl E. Swartzlander Jr. (ACSSC, 2013)

Improved Architectures for a Floating-Point Fused Dot Product Unit. - Jongwook Sohn; Earl E. Swartzlander Jr. (IEEE Symposium on Computer Arithmetic, 2013)

Truncated Logarithmic Approximation. - Michael B. Sullivan 001; Earl E. Swartzlander Jr. (IEEE Symposium on Computer Arithmetic, 2013)

Fused floating-point two-term sum-of-squares unit. - Jae Hong Min; Earl E. Swartzlander Jr. (ASAP, 2013)

The optimum Booth radix for low power integer multipliers. - Hani H. Saleh; Baker S. Mohammad; Earl E. Swartzlander Jr. (IDT, 2013)

Power analysis attack of QCA circuits: A case study of the Serpent cipher. - Weiqiang Liu 001; Saket Srivastava; Liang Lu; Máire O'Neill; Earl E. Swartzlander Jr. (ISCAS, 2013)

Improved non-restoring division algorithm with dual path calculation. - Kihwan Jun; Earl E. Swartzlander Jr. (MWSCAS, 2013)

Fused floating-point magnitude unit. - Jae Hong Min; Earl E. Swartzlander Jr. (MWSCAS, 2013)

STARS: Electronic Calculators: Desktop to Pocket. - Earl E. Swartzlander Jr. (Proc. IEEE, 2013)

QCA Systolic Array Design. - Liang Lu; Weiqiang Liu 001; Máire O'Neill; Earl E. Swartzlander Jr. (IEEE Trans. Computers, 2013)

Structure-Aware Placement Techniques for Designs With Datapaths. - Samuel I. Ward; Myung-Chul Kim; Natarajan Viswanathan; Zhuo Li 001; Charles J. Alpert; Earl E. Swartzlander Jr.; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

High-Speed Computer Arithmetic. - Earl E. Swartzlander Jr. (Computing Handbook, 3rd ed. (1), 2014)

Improved non-restoring square root algorithm with dual path calculation. - Kihwan Jun; Earl E. Swartzlander Jr. (ACSSC, 2014)

Memristor based adders. - Divya Mahajan 001; Matheen Musaddiq; Earl E. Swartzlander Jr. (ACSSC, 2014)

Design of Goldschmidt Dividers with Quantum-Dot Cellular Automata. - Inwook Kong; Seong-Wan Kim; Earl E. Swartzlander Jr. (IEEE Trans. Computers, 2014)

A Fused Floating-Point Three-Term Adder. - Jongwook Sohn; Earl E. Swartzlander Jr. (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Security Issues in QCA Circuit Design - Power Analysis Attacks. - Weiqiang Liu 001; Saket Srivastava; Máire O'Neill; Earl E. Swartzlander Jr. (Field-Coupled Nanocomputing, 2014)

Extreme multi-core, multi-network Java DataFlow Machine (JavaFlow). - Robert J. Ascott; Earl E. Swartzlander Jr. (ACSSC, 2015)

Exploiting asymmetry in Booth-encoded multipliers for reduced energy multiplication. - Mike O'Connor; Earl E. Swartzlander Jr. (ACSSC, 2015)

Low-Cost Duplicate Multiplication. - Michael B. Sullivan 001; Earl E. Swartzlander Jr. (ARITH, 2015)

Design of 3-D quantum-dot cellular automata adders. - Weiqiang Liu 001; Earl E. Swartzlander Jr. (IEICE Electron. Express, 2015)

Optimized memristor-based ripple carry adders. - Lauren Guckert; Earl E. Swartzlander Jr. (ACSSC, 2016)

Memristor based adder circuit design. - Nagaraja Revanna; Earl E. Swartzlander Jr. (ACSSC, 2016)

Arithmetic circuit design with memristor based high fan-out logic gates. - Nagaraja Revanna; Earl E. Swartzlander Jr. (UEMCON, 2016)

A Modified Partial Product Generator for Redundant Binary Multipliers. - Xiao-Ping Cui; Weiqiang Liu 001; Xin Chen 039; Earl E. Swartzlander Jr.; Fabrizio Lombardi (IEEE Trans. Computers, 2016)

A Fused Floating-Point Four-Term Dot Product Unit. - Jongwook Sohn; Earl E. Swartzlander Jr. (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Parallel GF(2n) multipliers. - Trenton J. Grale; Earl E. Swartzlander Jr. (ACSSC, 2017)

The future of computing - Arithmetic circuits implemented with memristors. - Nagaraja Revanna; Lauren Guckert; Earl E. Swartzlander Jr. (ACSSC, 2017)

Dadda Multiplier designs using memristors. - Lauren Guckert; Earl E. Swartzlander Jr. (ICICDT, 2017)

High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes. - Xiao-Ping Cui; Wenwen Dong; Weiqiang Liu 001; Earl E. Swartzlander Jr.; Fabrizio Lombardi (IEEE Trans. Computers, 2017)

Optimized Memristor-Based Multipliers. - Lauren Guckert; Earl E. Swartzlander Jr. (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

MAD Gates - Memristor Logic Design Using Driver Circuitry. - Lauren Guckert; Earl E. Swartzlander Jr. (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Guest Editorial: Introduction to the Special Issue on Emerging Technologies and Designs for Application-Specific Computing. - Weiqiang Liu 001; Earl E. Swartzlander Jr.; Máire O'Neill (IEEE Trans. Emerg. Top. Comput., 2017)

Memristor Adder Design. - Nagaraja Revanna; Earl E. Swartzlander Jr. (MWSCAS, 2018)

Memristor-Based Computing. - Lizy K. John; Earl E. Swartzlander Jr. (IEEE Micro, 2018)

Data Compression Device Based on Modified LZ4 Algorithm. - Weiqiang Liu 001; Faqiang Mei; Chenghua Wang; Máire O'Neill; Earl E. Swartzlander Jr. (IEEE Trans. Consumer Electron., 2018)

Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders. - Xiao-Ping Cui; Weiqiang Liu 001; Shumin Wang; Earl E. Swartzlander Jr.; Fabrizio Lombardi (J. Signal Process. Syst., 2018)

Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications. - Peipei Yin; Chenghua Wang; Weiqiang Liu 001; Earl E. Swartzlander Jr.; Fabrizio Lombardi (J. Signal Process. Syst., 2018)

Memristor-Based Addition and Multiplication. - K'Andrea C. Bickerstaff; Earl E. Swartzlander Jr. (Handbook of Memristor Networks, 2019)

A Variable-Latency Architecture for Accelerating Deterministic Approaches to Stochastic Computing. - Alexander J. Groszewski; Earl E. Swartzlander Jr. (ACSSC, 2019)

Parallel GF(2n) Modular Squarers. - Trenton J. Grale; Earl E. Swartzlander Jr. (MWSCAS, 2019)

Design and Analysis of Approximate Redundant Binary Multipliers. - Weiqiang Liu 001; Tian Cao 005; Peipei Yin; Yuying Zhu 003; Chenghua Wang; Earl E. Swartzlander Jr.; Fabrizio Lombardi (IEEE Trans. Computers, 2019)

A Bfloat16 Fused Multiplier-Adder. - Stafford Hutchins; Earl E. Swartzlander Jr. (UEMCON, 2020)

LogGen: A Parameterized Generator for Designing Floating-Point Logarithm Units for Deep Learning. - Pragnesh Patel; Aman Arora 001; Earl E. Swartzlander Jr.; Lizy K. John (ISQED, 2022)

Improved Montgomery Multiplication. - Trenton J. Grale; Earl E. Swartzlander Jr. (ARITH, 2023)