Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning. - Steve Dai; Yuan Zhou; Hang Zhang 010; Ecenur Ustun; Evangeline F. Y. Young; Zhiru Zhang (FCCM, 2018)

DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only). - Gai Liu; Ecenur Ustun; Shaojie Xiang; Chang Xu 005; Guojie Luo; Zhiru Zhang (FPGA, 2018)

LAMDA: Learning-Assisted Multi-stage Autotuning for FPGA Design Closure. - Ecenur Ustun; Shaojie Xiang; Jinny Gui; Cunxi Yu; Zhiru Zhang (FCCM, 2019)

Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks. - Ecenur Ustun; Chenhui Deng; Debjit Pal; Zhijing Li 002; Zhiru Zhang (ICCAD, 2020)

AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. - Licheng Guo; Yuze Chi; Jie Wang 022; Jason Lau; Weikang Qiao; Ecenur Ustun; Zhiru Zhang; Jason Cong (FPGA, 2021)

GraphLily: Accelerating Graph Linear Algebra on HBM-Equipped FPGAs. - Yuwei Hu; Yixiao Du; Ecenur Ustun; Zhiru Zhang (ICCAD, 2021)

Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects. - Yi-Hsiang Lai; Ecenur Ustun; Shaojie Xiang; Zhenman Fang; Hongbo Rong; Zhiru Zhang (ACM Trans. Reconfigurable Technol. Syst., 2021)

IMpress: Large Integer Multiplication Expression Rewriting for FPGA HLS. - Ecenur Ustun; Ismail San; Jiaqi Yin; Cunxi Yu; Zhiru Zhang (FCCM, 2022)

Equality Saturation for Datapath Synthesis: A Pathway to Pareto Optimality. - Ecenur Ustun; Cunxi Yu; Zhiru Zhang (DAC, 2023)

TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design. - Licheng Guo; Yuze Chi; Jason Lau; Linghao Song; Xingyu Tian; Moazin Khatti; Weikang Qiao; Jie Wang 022; Ecenur Ustun; Zhenman Fang; Zhiru Zhang; Jason Cong (ACM Trans. Reconfigurable Technol. Syst., 2023)