Issues in the implementation of the i486TM cache and bus. - Ed Grochowski; Ken Shoemaker (ICCD, 1989)

Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation. - Ed Grochowski; David Ayers; Vivek Tiwari (HPCA, 2002)

Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. - Perry H. Wang; Hong Wang 003; Jamison D. Collins; Ed Grochowski; Ralph-Michael Kling; John Paul Shen (HPCA, 2002)

Microarchitectural dI/dt Control. - Ed Grochowski; David Ayers; Vivek Tiwari (IEEE Des. Test Comput., 2003)

Best of Both Latency and Throughput. - Ed Grochowski; Ronny Ronen; John Paul Shen; Hong Wang 003 (ICCD, 2004)

Mitigating Amdahl's Law through EPI Throttling. - Murali Annavaram; Ed Grochowski; John Paul Shen (ISCA, 2005)

Implications of device timing variability on full chip timing. - Ed Grochowski; Murali Annavaram; Paul Reed (ISPD, 2008)

Larrabee: A Many-Core x86 Architecture for Visual Computing. - Larry Seiler; Doug Carmean; Eric Sprangle; Tom Forsyth; Pradeep Dubey; Stephen Junkins; Adam T. Lake; Robert Cavin; Roger Espasa; Ed Grochowski; Toni Juan; Michael Abrash; et al. (IEEE Micro, 2009)

Performance Benefits of Heterogeneous Computing in HPC Workloads. - Victor W. Lee; Ed Grochowski; Robert Geva (IPDPS Workshops, 2012)

Improving the energy efficiency of Big Cores. - Kenneth Czechowski; Victor W. Lee; Ed Grochowski; Ronny Ronen; Ronak Singhal; Richard W. Vuduc; Pradeep Dubey (ISCA, 2014)