AM suppression with low AM-PM conversion with the aid of a variable-gain amplifier. - Eric A. M. Klumperink; Carlo T. Klein; Bas Rüggeberg; Ed J. M. van Tuijl (IEEE J. Solid State Circuits, 1996)

A low noise, low residual offset, chopped amplifier for mixed level applications. - Mihai A. T. Sanduleanu; A. J. M. van Tuijl; R. F. Wassenaar; M. C. Lammers; H. Wallinga (ICECS, 1998)

Intrinsic 1/f device noise reduction and its effect on phase noise in CMOS ring oscillators. - Sander L. J. Gierkink; Eric A. M. Klumperink; Arnoud P. van der Wel; Gian Hoogzaad; Ed A. J. M. van Tuijl; Bram Nauta (IEEE J. Solid State Circuits, 1999)

A power-efficient audio amplifier combining switching and linear techniques. - Ronan A. R. van der Zee; Ed A. J. M. van Tuijl (IEEE J. Solid State Circuits, 1999)

A coupled sawtooth oscillator combining low jitter with high control linearity. - Sander L. J. Gierkink; Ed van Tuijl (IEEE J. Solid State Circuits, 2002)

A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS [ADC applications]. - Simon M. Louwsma; Ed J. M. van Tuijl; Maarten Vertregt; Peter C. S. Scholtens; Bram Nauta (ESSCIRC, 2004)

Reducing quantization noise with recursive Sigma Delta modulators. - Daniël Schinkel; Ed van Tuijl; Anne-Johan Annema (ISCAS (1), 2004)

An audio FIR-DAC in a BCD process for high power class-D amplifiers. - T. S. Doorn; Ed van Tuijl; Daniël Schinkel; Anne-Johan Annema; Marco Berkhout; Bram Nauta (ESSCIRC, 2005)

Optimally-placed twists in global on-chip differential interconnects. - Eisse Mensink; Daniël Schinkel; Eric A. M. Klumperink; Ed van Tuijl; Bram Nauta (ESSCIRC, 2005)

A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects. - Daniël Schinkel; Eisse Mensink; Eric A. M. Klumperink; Ed J. M. van Tuijl; Bram Nauta (IEEE J. Solid State Circuits, 2006)

A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR. - Simon M. Louwsma; Ed van Tuijl; Maarten Vertregt; Bram Nauta (CICC, 2007)

A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects. - Eisse Mensink; Daniël Schinkel; Eric A. M. Klumperink; Ed van Tuijl; Bram Nauta (ISSCC, 2007)

A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time. - Daniël Schinkel; Eisse Mensink; Eric A. M. Klumperink; Ed van Tuijl; Bram Nauta (ISSCC, 2007)

Optimal Positions of Twists in Global On-Chip Differential Interconnects. - Eisse Mensink; Daniël Schinkel; Eric A. M. Klumperink; Ed van Tuijl; Bram Nauta (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Session 20 - Advanced wireline techniques. - Ed van Tuijl; Ken Chang (CICC, 2008)

Audio at low and high power. - Marco Berkhout; Lucien J. Breems; Ed van Tuijl (ESSCIRC, 2008)

A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC. - Michiel van Elzakker; Ed van Tuijl; Paul F. J. Geraedts; Daniël Schinkel; Eric A. M. Klumperink; Bram Nauta (ISSCC, 2008)

A 90μW 12MHz Relaxation Oscillator with a -162dB FOM. - Paul F. J. Geraedts; Ed van Tuijl; Eric A. M. Klumperink; Gerard Wienk; Bram Nauta (ISSCC, 2008)

A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS. - Simon M. Louwsma; A. J. M. van Tuijl; Maarten Vertregt; Bram Nauta (IEEE J. Solid State Circuits, 2008)

Low-Power, High-Speed Transceivers for Network-on-Chip Communication. - Daniël Schinkel; Eisse Mensink; Eric A. M. Klumperink; Ed van Tuijl; Bram Nauta (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A 10-bit Charge-Redistribution ADC Consuming 1.9 μ W at 1 MS/s. - Michiel van Elzakker; Ed van Tuijl; Paul F. J. Geraedts; Daniël Schinkel; Eric A. M. Klumperink; Bram Nauta (IEEE J. Solid State Circuits, 2010)

Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects. - Eisse Mensink; Daniël Schinkel; Eric A. M. Klumperink; Ed van Tuijl; Bram Nauta (IEEE J. Solid State Circuits, 2010)

A narrow-to-wideband scrambling technique increasing software radio receiver linearity. - Fabian van Houwelingen; Ed van Tuijl; Bram Nauta; Maarten Vertregt (ESSCIRC, 2011)

Towards minimum achievable phase noise of relaxation oscillators. - Paul F. J. Geraedts; Ed J. M. van Tuijl; Eric A. M. Klumperink; Gerard J. M. Wienk; Bram Nauta (Int. J. Circuit Theory Appl., 2014)

Session 5 overview: Analog techniques: Analog subcommittee. - Xicheng Jiang; Ed van Tuijl (ISSCC, 2015)

15.3 A 115dB-DR audio DAC with -61dBFS out-of-band noise. - Hugo Westerveld; Daniël Schinkel; Ed van Tuijl (ISSCC, 2015)

Range pre-selection sampling technique to reduce input drive energy for SAR ADCs. - Harijot Singh Bindra; Joeri Lechevallier; Anne-Johan Annema; Simon M. Louwsma; Ed van Tuijl; Bram Nauta (A-SSCC, 2017)

An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC. - Harijot Singh Bindra; Anne-Johan Annema; Simon M. Louwsma; Ed J. M. van Tuijl; Bram Nauta (ESSCIRC, 2017)