A configurable and programmable motion estimation processor for the H.264 video codec. - José Luis Núñez-Yáñez; Eddie Hung; Vassilios A. Chouliaras (FPL, 2008)

A detailed delay path model for FPGAs. - Eddie Hung; Steven J. E. Wilton; Haile Yu; Thomas C. P. Chau; Philip Heng Wai Leong (FPT, 2009)

Speculative Debug Insertion for FPGAs. - Eddie Hung; Steven J. E. Wilton (FPL, 2011)

On evaluating signal selection algorithms for post-silicon debug. - Eddie Hung; Steven J. E. Wilton (ISQED, 2011)

Limitations of incremental signal-tracing for FPGA debug. - Eddie Hung; Steven J. E. Wilton (FPL, 2012)

Rapid RTL-based signal ranking for FPGA prototyping. - Steven J. E. Wilton; Bradley R. Quinton; Eddie Hung (FPT, 2012)

Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding. - José Luis Núñez-Yáñez; Atukem Nabina; Eddie Hung; George Vafiadis (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices. - Eddie Hung; Fatemeh Eslami; Steven J. E. Wilton (FCCM, 2013)

Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers. - Eddie Hung; Steven J. E. Wilton (FPGA, 2013)

Maximum flow algorithms for maximum observability during FPGA debug. - Eddie Hung; Al-Shahna Jamal; Steven J. E. Wilton (FPT, 2013)

Linking the Verification and Validation of Complex Integrated Circuits Through Shared Coverage Metrics. - Eddie Hung; Bradley R. Quinton; Steven J. E. Wilton (IEEE Des. Test, 2013)

Scalable Signal Selection for Post-Silicon Debug. - Eddie Hung; Steven J. E. Wilton (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry. - Eddie Hung; Jeffrey B. Goeders; Steven J. E. Wilton (ARC, 2014)

Transparent insertion of latency-oblivious logic onto FPGAs. - Eddie Hung; Tim Todman; Wayne Luk (FPL, 2014)

Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network. - Eddie Hung; Steven J. E. Wilton (ACM Trans. Design Autom. Electr. Syst., 2014)

Incremental Trace-Buffer Insertion for FPGA Debug. - Eddie Hung; Steven J. E. Wilton (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Accelerating SpMV on FPGAs by Compressing Nonzero Values. - Paul Grigoras; Pavel Burovskiy; Eddie Hung; Wayne Luk (FCCM, 2015)

Delay-Bounded Routing for Shadow Registers. - Eddie Hung; Joshua M. Levine; Edward A. Stott; George A. Constantinides; Wayne Luk (FPGA, 2015)

Mind the (synthesis) gap: Examining where academic FPGA tools lag behind industry. - Eddie Hung (FPL, 2015)

KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. - Eddie Hung; James J. Davis 001; Joshua M. Levine; Edward A. Stott; Peter Y. K. Cheung; George A. Constantinides (FCCM, 2016)

Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). - James J. Davis 001; Eddie Hung; Joshua M. Levine; Edward A. Stott; Peter Y. K. Cheung; George A. Constantinides (FPGA, 2016)

Enabling Effective FPGA Debug using Overlays: Opportunities and Challenges. - Fatemeh Eslami; Eddie Hung; Steven J. E. Wilton (CoRR, 2016)

STRIPE: Signal selection for runtime power estimation. - James J. Davis 001; Joshua M. Levine; Edward A. Stott; Eddie Hung; Peter Y. K. Cheung; George A. Constantinides (FPL, 2017)

KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications. - James J. Davis 001; Joshua M. Levine; Edward A. Stott; Eddie Hung; Peter Y. K. Cheung; George A. Constantinides (IEEE Des. Test, 2017)

Transparent In-Circuit Assertions for FPGAs. - Eddie Hung; Tim Todman; Wayne Luk (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Extending post-silicon coverage measurement using time-multiplexed FPGA overlays. - Fatemeh Eslami; Eddie Hung; Steven J. E. Wilton (ETS, 2018)

KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications. - James J. Davis 001; Joshua M. Levine; Edward A. Stott; Eddie Hung; Peter Y. K. Cheung; George A. Constantinides (IWOCL, 2018)

KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. - James J. Davis 001; Eddie Hung; Joshua M. Levine; Edward A. Stott; Peter Y. K. Cheung; George A. Constantinides (ACM Trans. Reconfigurable Technol. Syst., 2018)

EFCAD - An Embedded FPGA CAD Tool Flow for Enabling On-chip Self-Compilation. - Khoa Dang Pham; Malte Vesper; Dirk Koch; Eddie Hung (FCCM, 2019)

Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs. - David Shah; Eddie Hung; Clifford Wolf; Serge Bazanski; Dan Gisselquist; Miodrag Milanovic (FCCM, 2019)

100% Visibility at MHz Speed: Efficient Soft Scan-Chain Insertion on AMD/Xilinx FPGAs. - Hossein Omidian; Eddie Hung; Dinesh Gaitonde (ARC, 2022)

Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry. - Benjamin Lukas Cajus Barzen; Arya Reais-Parsi; Eddie Hung; Minwoo Kang; Alan Mishchenko; Jonathan W. Greene; John Wawrzynek (DATE, 2023)

Invited Paper: RapidWright: Unleashing the Full Power of FPGA Technology with Domain-Specific Tooling. - Chris Lavin; Eddie Hung (ICCAD, 2023)

RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. - Licheng Guo; Pongstorn Maidee; Yun Zhou; Chris Lavin; Eddie Hung; Wuxi Li; Jason Lau; Weikang Qiao; Yuze Chi; Linghao Song; Yuanlong Xiao; Alireza Kaviani; et al. (ACM Trans. Reconfigurable Technol. Syst., 2023)

DynaRapid: Fast-Tracking from C to Routed Circuits. - Andrea Guerrieri; Srijeet Guha; Chris Lavin; Eddie Hung; Lana Josipovic; Paolo Ienne (FPL, 2024)