Backplane/FDA correlation-FDA replacing commercial backplanes for SoC ethernet electrical validation. - Jesus-Andres Mendoza-Bonilla; Alejandro Cortez-Ibarra; Edgar-Andrei Vega-Ochoa; Francisco Rangel-Patino; Brandon Gore (VLSI-SoC, 2014)

SMV methodology enhancements for high speed I/O links of SoCs. - Andres Viveros-Wacher; Ricardo Alejos; Liliana Alvarez; Israel Diaz-Castro; Brenda Marcial; Gaston Motola-Acuna; Edgar-Andrei Vega-Ochoa (VTS, 2014)

Jitter tolerance acceleration using the golden section optimization technique. - Andres Viveros-Wacher; Ricardo Baca-Baylon; Francisco E. Rangel-Patino; Miguel A. Davalos-Santana; Edgar-Andrei Vega-Ochoa; José Ernesto Rayas-Sánchez (LASCAS, 2018)

Direct optimization of a PCI express link equalization in industrial post-silicon validation. - Francisco E. Rangel-Patino; José Ernesto Rayas-Sánchez; Edgar-Andrei Vega-Ochoa; Nagib Hakim (LATS, 2018)

Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks. - Francisco E. Rangel-Patino; José Ernesto Rayas-Sánchez; Andres Viveros-Wacher; José Luis Chavez-Hurtado; Edgar-Andrei Vega-Ochoa; Nagib Hakim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation. - Francisco E. Rangel-Patino; Andres Viveros-Wacher; José Ernesto Rayas-Sánchez; Ismael Duron-Rosales; Edgar-Andrei Vega-Ochoa; Nagib Hakim; Enrique Lopez-Miralrio (IEEE Trans. Emerg. Top. Comput., 2020)