From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. - Ney Laert Vilar Calazans; Edson I. Moreno; Fabiano Hessel; Vitor M. da Rosa; Fernando Moraes 001; Everton Carara (SBCCI, 2003)

Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture. - Alexandre M. Amory; Marcelo Lubaszewski; Fernando Gehm Moraes; Edson I. Moreno (DATE, 2005)

Evaluation of Algorithms for Low Energy Mapping onto NoCs. - César A. M. Marcon; Edson I. Moreno; Ney Laert Vilar Calazans; Fernando Gehm Moraes (ISCAS, 2007)

Integrating Abstract NoC Models within MPSoC Design. - Edson Ifarraguirre Moreno; Katalin Maria Popovici; Ney Laert Vilar Calazans; Ahmed Amine Jerraya (IEEE International Workshop on Rapid System Prototyping, 2008)

Comparison of network-on-chip mapping algorithms targeting low energy consumption. - César Augusto Missio Marcon; Edson Ifarraguirre Moreno; Ney Laert Vilar Calazans; Fernando Gehm Moraes (IET Comput. Digit. Tech., 2008)

Mapeamento e adaptação de rotas de comunicação em redes em chip. - Edson Ifarraguirre Moreno (2010)

Arbitration and routing impact on NoC design. - Edson I. Moreno; César A. M. Marcon; Ney Laert Vilar Calazans; Fernando Gehm Moraes (International Symposium on Rapid System Prototyping, 2011)

CAFES: A framework for intrachip application modeling and communication architecture design. - César A. M. Marcon; Ney Calazans; Edson I. Moreno; Fernando Moraes 001; Fabiano Hessel; Altamiro Amadeu Susin (J. Parallel Distributed Comput., 2011)

Buffer depth and traffic influence on 3D NoCs performance. - Yan Ghidini; Thais Webber; Edson I. Moreno; Fernando Grando; Rubem Dutra Ribeiro Fagundes; César A. M. Marcon (RSP, 2012)

Topological impact on latency and throughput: 2D versus 3D NoC comparison. - Yan Ghidini; Thais Webber; Edson I. Moreno; Ivan Quadros; Rubem Dutra Ribeiro Fagundes; César A. M. Marcon (SBCCI, 2012)

Determining the test sources/sinks for NoC TAMs. - Alexandre M. Amory; Edson I. Moreno; Fernando Moraes 001; Marcelo Lubaszewski (ISVLSI, 2013)

A monitored NoC with runtime path adaptation. - Edson I. Moreno; Thais Webber; César A. M. Marcon; Fernando Moraes 001; Ney Calazans (ISCAS, 2014)

MoNoC: A monitored network on chip with path adaptation mechanism. - Edson I. Moreno; Thais Webber; César A. M. Marcon; Fernando Gehm Moraes; Ney Laert Vilar Calazans (J. Syst. Archit., 2014)