Modeling of Short Circuit Power Consumption Using Timing-Only Logic Cell Macromodels. - Eduardo A. C. da Costa; Fernando Paixão Cortes; Rodrigo Ferrugem Cardoso; Luigi Carro; Sergio Bampi (SBCCI, 2000)

Power Efficient Arithmetic Operand Encoding. - Eduardo Costa 001; Sergio Bampi; José Monteiro 001 (SBCCI, 2001)

A New Architecture for Signed Radix-2m Pure Array Multipliers. - Eduardo A. C. da Costa; Sergio Bampi; José Monteiro 001 (ICCD, 2002)

A New Architecture for 2's Complement Gray Encoded Array Multiplier. - Eduardo Costa 001; Sergio Bampi; José Monteiro 001 (SBCCI, 2002)

A New Pipelined Array Architecture for Signed Multiplication. - Eduardo A. C. da Costa; Sergio Bampi; José Monteiro 001 (SBCCI, 2003)

Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths. - Eduardo A. C. da Costa; José C. Monteiro 001; Sergio Bampi (VLSI-SoC (Selected Papers), 2003)

An improved synthesis method for low power hardwired FIR filters. - Vagner S. Rosa; Eduardo A. C. da Costa; José C. Monteiro 001; Sergio Bampi (SBCCI, 2004)

Maximal sharing of partial terms in MCM under minimal signed digit representation. - Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (ECCTD, 2005)

An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications. - Paulo F. Flores; José Monteiro 001; Eduardo A. C. da Costa (ICCAD, 2005)

Design of a radix-2m hybrid array multiplier using carry save adder format. - Mateus Fonseca; Eduardo A. C. da Costa; Sergio Bampi; José Monteiro 001 (SBCCI, 2005)

A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures. - Leonardo Londero de Oliveira; Cristiano Santos; Daniel Lima Ferrão; Eduardo A. C. da Costa; José Monteiro 001; João Baptista dos Santos Martins; Sergio Bampi; Ricardo Augusto da Luz Reis (VLSI-SoC, 2005)

Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming. - Levent Aksoy; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (DAC, 2006)

ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ICECS, 2006)

A High Performance Parallel FIR Filters Generation Tool. - Vagner S. Rosa; Eduardo A. C. da Costa; Sergio Bampi (IEEE International Workshop on Rapid System Prototyping, 2006)

Exploiting general coefficient representation for the optimal sharing of partial products in MCMs. - Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (SBCCI, 2006)

A VHDL Generation Tool for Optimized Parallel FIR Filters. - Vagner S. Rosa; Eduardo A. C. da Costa; Sergio Bampi (VLSI-SoC, 2006)

Optimization of Area in Digital FIR Filters using Gate-Level Metrics. - Levent Aksoy; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (DAC, 2007)

Minimum number of operations under a general number representation for digital filter synthesis. - Levent Aksoy; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (ECCTD, 2007)

Effect of Number Representation on the Achievable Minimum Number of Operations in Multiple Constant Multiplications. - Levent Aksoy; Ece Olcay Günes; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (SiPS, 2007)

A new array architecture for signed multiplication using Gray encoded radix-2m operands. - Eduardo A. C. da Costa; José Monteiro 001; Sergio Bampi (Integr., 2007)

Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications. - Levent Aksoy; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Power efficient architecture for motion estimation using the QSDS-DIC algorithm. - Marcelo Schiavon Porto; Sergio Bampi; João S. Altermann; Eduardo Costa 001 (ICECS, 2009)

Design flow for the generation of optimized FIR filters. - Vagner S. Rosa; Fabio F. Daitx; Eduardo Costa 001; Sergio Bampi (ICECS, 2009)

Design of low complexity digital FIR filters. - Levent Aksoy; Diego Jaccottet; Eduardo Costa 001 (SBCCI, 2009)

High performance motion estimation architecture using efficient adder-compressors. - André Silva; Eduardo A. C. da Costa; Sérgio J. M. de Almeida; Marcelo Schiavon Porto; Sergio Bampi (SBCCI, 2009)

Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (DSD, 2010)

Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach. - Sidinei Ghissoni; Eduardo Costa 001; Cristiano Lazzari; José Monteiro 001; Levent Aksoy; Ricardo Reis 001 (ICECS, 2010)

Performance enhancement of H.264/AVC intra frame prediction hardware using efficient 4-2 and 5-2 adder-compressors. - Cláudio Machado Diniz; João S. Altermann; Eduardo A. C. da Costa; Sergio Bampi (SBCCI, 2010)

Ordering and partitioning of coefficients based on heuristic algorithms for low power FIR filter realization. - Angelo G. da Luz; Eduardo A. C. da Costa; Marilton S. de Aguiar (SBCCI, 2010)

Fast forward and inverse transforms for the H.264/AVC standard using hierarchical adder compressors. - João S. Altermann; Eduardo A. C. da Costa; Sergio Bampi (VLSI-SoC, 2010)

Design of low-complexity and high-speed digital Finite Impulse Response filters. - Diego Jaccottet; Eduardo Costa 001; Levent Aksoy; Paulo F. Flores; José Monteiro 001 (VLSI-SoC, 2010)

Efficient Dedicated Multiplication Blocks for 2's Complement Radix-2m Array Multipliers. - Leandro Zafalon Pieper; Eduardo A. C. da Costa; Sérgio J. M. de Almeida; Sergio Bampi; José C. Monteiro 001 (J. Comput., 2010)

Optimization of gate-level area in high throughput Multiple Constant Multiplications. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ECCTD, 2011)

High performance Haar Wavelet transform architecture. - João S. Altermann; Eduardo A. C. da Costa; Sérgio J. M. de Almeida (ECCTD, 2011)

Design of low-power multiple constant multiplications using low-complexity minimum depth operations. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ACM Great Lakes Symposium on VLSI, 2011)

Efficient shift-adds design of digit-serial multiple constant multiplications. - Levent Aksoy; Cristiano Lazzari; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ACM Great Lakes Symposium on VLSI, 2011)

Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization. - Sidinei Ghissoni; Eduardo Costa 001; José Monteiro 001; Ricardo Reis 001 (ICECS, 2011)

Optimization of area in digit-serial Multiple Constant Multiplications at gate-level. - Levent Aksoy; Cristiano Lazzari; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ISCAS, 2011)

Exploring the use of heuristic-based algorithms for the ordering and partitioning of coefficients for power efficient fir filters realization. - Angelo G. da Luz; Eduardo A. C. da Costa; Marilton S. de Aguiar (SBCCI, 2011)

A hybrid algorithm for the optimization of area and delay in linear DSP transforms. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (VLSI-SoC, 2011)

Multiplierless Design of Linear DSP Transforms. - Levent Aksoy; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (VLSI-SoC (Selected Papers), 2011)

Finding the optimal tradeoff between area and delay in multiple constant multiplications. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (Microprocess. Microsystems, 2011)

Design of low-complexity digital finite impulse response filters on FPGAs. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (DATE, 2012)

Multiple tunable constant multiplications: Algorithms and applications. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ICCAD, 2012)

Efficient area and power multiplication part of FFT based on twiddle factor decomposition. - Sidinei Ghissoni; Eduardo Costa 001; José Monteiro 001; Ricardo Reis 001 (ICECS, 2012)

High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications. - Levent Aksoy; Cristiano Lazzari; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (Integr., 2012)

Optimization Algorithms for the Multiplierless Realization of Linear Transforms. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ACM Trans. Design Autom. Electr. Syst., 2012)

Exploration of tradeoffs in the design of integer cosine transforms for image compression. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ECCTD, 2013)

Design of an efficient FPGA-based interference canceller structure using NLMS adaptive algorithm. - Eduardo A. C. da Costa; Sérgio J. M. de Almeida (ICECS, 2013)

Reducing switching activity in FIR filters by reordering the coefficients through the use of improved heuristic algorithm. - João G. Nizer Rahmeier; Angelo G. da Luz; Eduardo A. C. da Costa; Sidinei Ghissoni (ICECS, 2013)

Reducing the Hamming distance of encoded FFT twiddle factors using improved heuristic algorithms. - Angelo Goncalves da Luz; Eduardo A. C. da Costa; Sidinei Ghissoni (LASCAS, 2013)

Fixed-point adaptive filter architecture for the harmonics power line interference cancelling. - Gustavo Seibel; Fábio P. Itturriet; Eduardo Costa 001; Sérgio Almeida 001 (LASCAS, 2013)

Gray encoded fixed-point LMS adaptive filter architecture for the harmonics power line interference cancelling. - Eduardo A. C. da Costa; Sérgio J. M. de Almeida; Monica Matzenauer (SBCCI, 2013)

Combination of radix-2m multiplier blocks and adder compressors for the design of efficient 2's complement 64-bit array multipliers. - Leandro Zafalon Pieper; Eduardo A. C. da Costa; José C. Monteiro 001 (SBCCI, 2013)

Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool. - Levent Aksoy; Cristiano Lazzari; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Implementation of power efficient multicore FFT datapaths by reordering the twiddle factors. - Sidinei Ghissoni; Eduardo A. C. da Costa; Angelo Goncalves da Luz (VLSI-SoC, 2014)

Floating-point adaptive filter architectures for the cancelling of harmonics power line interference. - Vagner Guidotti; Eduardo A. C. da Costa; Sérgio J. M. de Almeida; Mateus Fonseca (ICECS, 2015)

Energy-efficient Gaussian filter for image processing using approximate adder circuits. - Julio F. R. Oliveira; Leonardo Bandeira Soares; Eduardo A. C. da Costa; Sergio Bampi (ICECS, 2015)

Optimal combination of dedicated multiplication blocks and adder trees schemes for optimized radix-2m array multipliers realization. - Anderson Martins; Mateus Fonseca; Eduardo A. C. da Costa (ICECS, 2015)

Power efficient 2-D rounded cosine transform with adder compressors for image compression. - Guilherme Paim; Mateus Fonseca; Eduardo A. C. da Costa; Sérgio J. M. de Almeida (ICECS, 2015)

SATD hardware architecture based on 8×8 Hadamard Transform for HEVC encoder. - Bianca Silveira; Cláudio Machado Diniz; Mateus Fonseca; Eduardo A. C. da Costa (ICECS, 2015)

Enhancing a HEVC interpolation filter hardware architecture with efficient adder compressors. - Cláudio Machado Diniz; Mateus Beck Fonseca; Eduardo A. C. da Costa; Sergio Bampi (NEWCAS, 2015)

Approximate adder synthesis for area- and energy-efficient FIR filters in CMOS VLSI. - Leonardo Bandeira Soares; Sergio Bampi; Eduardo Costa 001 (NEWCAS, 2015)

Near-threshold computing for very wide frequency scaling: Approximate adders to rescue performance. - Leonardo Bandeira Soares; Sergio Bampi; Andre Luis Rodeghiero Rosa; Eduardo A. C. da Costa (NEWCAS, 2015)

Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs. - Sidinei Ghissoni; Eduardo Costa 001; Ricardo Reis 001 (PATMOS, 2015)

A power-efficient imprecise radix-4 multiplier applied to high resolution audio processing. - Guilherme Paim; Leonardo Bandeira Soares; Julio F. R. Oliveira; Eduardo Costa 001; Sergio Bampi (ICECS, 2016)

Power-efficient sum of absolute differences architecture using adder compressors. - Bianca Silveira; Guilherme Paim; Cláudio Machado Diniz; Eduardo A. C. da Costa (ICECS, 2016)

Design of optimized radix-2 and radix-4 butterflies from FFT with decimation in time. - Renato Neuenfeld; Mateus Fonseca; Eduardo A. C. da Costa (LASCAS, 2016)

Exploiting approximate adder circuits for power-efficient Gaussian and Gradient filters for Canny edge detector algorithm. - Julio de Oliveira 001; Leonardo Bandeira Soares; Eduardo Costa 001; Sergio Bampi (LASCAS, 2016)

Exploiting architectural solutions for IIR filter architecture with truncation error feedback. - Gustavo Ott; Eduardo A. C. da Costa; Sérgio J. M. de Almeida; Mateus Fonseca (LASCAS, 2016)

Exploiting adder compressors for power-efficient 2-D approximate DCT realization. - Tiago Schiavon; Guilherme Paim; Mateus Fonseca; Eduardo A. C. da Costa; Sérgio J. M. de Almeida (LASCAS, 2016)

Using adder compressors for power-efficient 2-D approximate Discrete Tchebichef Transform. - Guilherme Paim; Eduardo A. C. da Costa (NEWCAS, 2016)

A novel pruned-based algorithm for energy-efficient SATD operation in the HEVC coding. - Leonardo Bandeira Soares; Cláudio Machado Diniz; Eduardo Antonio Cesar da Costa; Sergio Bampi (SBCCI, 2016)

Exploiting absolute arithmetic for power-efficient sum of absolute differences. - Brunno Abreu; Guilherme Paim; Mateus Grellert; Bianca Silveira; Cláudio Machado Diniz; Eduardo Costa 001; Sergio Bampi (ICECS, 2017)

Exploring the use of parallel prefix adder topologies into approximate adder circuits. - Morgana Macedo; Leonardo Bandeira Soares; Bianca Silveira; Cláudio Machado Diniz; Eduardo A. C. da Costa (ICECS, 2017)

Improved goldschmidt algorithm for fast and energy-efficient fixed-point divider. - Guilherme Paim; Pedro Marques; Eduardo A. C. da Costa; Sérgio J. M. de Almeida; Sergio Bampi (ICECS, 2017)

Framework-based arithmetic core generation to explore ASIC-based parallel binary multipliers. - Leandro M. G. Rocha; Guilherme Paim; Rafael S. Ferreira; Eduardo Costa 001; Sergio Bampi (ICECS, 2017)

Physical implementation of an ASIC-oriented SRAM-based viterbi decoder. - Leandro M. G. Rocha; Guilherme Paim; Gustavo M. Santana; Brunno A. Abreu; Rafael Ferreira 001; Eduardo A. C. da Costa; Sergio Bampi (ICECS, 2017)

Using efficient adder compressors with a split-radix butterfly hardware architecture for low-power IoT smart sensors. - Gustavo M. Santana; Guilherme Paim; Leandro M. G. Rocha; Renato Neuenfeld; Mateus Beck Fonseca; Eduardo A. C. da Costa; Sergio Bampi (ICECS, 2017)

Exploring the combination of number of bits and number of iterations for a power-efficient fixed-point CORDIC implementation. - Andre N. Sapper; Leonardo Bandeira Soares; Eduardo Costa 001; Sergio Bampi (ICECS, 2017)

Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding. - Bianca Silveira; Brunno Abreu; Guilherme Paim; Mateus Grellert; Rafael S. Ferreira; Cláudio Machado Diniz; Eduardo Costa 001; Sergio Bampi (ICECS, 2017)

Low power sum of absolute differences architecture using novel hybrid adder. - Rafael Ferreira 001; Bianca Silveira; Mateus Beck Fonseca; Cláudio Machado Diniz; Eduardo A. C. da Costa (LASCAS, 2017)

Exploiting addition schemes for the improvement of optimized radix-2 and radix-4 fft butterflies. - Renato H. Neuenfeld; Mateus Beck Fonseca; Eduardo A. C. da Costa; Jean P. Oses (LASCAS, 2017)

A power-efficient 4-2 Adder Compressor topology. - Raphael Dornelles; Guilherme Paim; Bianca Silveira; Mateus Fonseca; Eduardo A. C. da Costa; Sergio Bampi (NEWCAS, 2017)

Pruning and approximation of coefficients for power-efficient 2-D Discrete Tchebichef Transform. - Guilherme Paim; Leonardo Bandeira Soares; Rafael S. Ferreira; Eduardo Costa 001; Sergio Bampi (NEWCAS, 2017)

Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors. - Bianca Silveira; Rafael S. Ferreira; Guilherme Paim; Cláudio Machado Diniz; Eduardo A. C. da Costa (NEWCAS, 2017)

A power-predictive environment for fast and power-aware ASIC-based FIR filter design. - Guilherme Paim; Rafael S. Ferreira; Leandro M. G. Rocha; Eduardo A. C. da Costa; Tiago Giacomelli Alves; Sergio Bampi (SBCCI, 2017)

Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design. - Bianca Silveira; Guilherme Paim; Brunno Abreu; Mateus Grellert; Cláudio Machado Diniz; Eduardo A. C. da Costa; Sergio Bampi (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Exploring power-performance-quality tradeoff of approximate adders for energy efficient sobel filtering. - Leonardo Bandeira Soares; Morgana M. A. da Rosa; Cláudio Machado Diniz; Eduardo A. C. da Costa; Sergio Bampi (LASCAS, 2018)

Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors. - Luis F. Sequeira; Gustavo M. Santana; Guilherme Paim; Leandro M. G. Rocha; Brunno Abreu; Eduardo Costa 001; Sergio Bampi (NEWCAS, 2018)

Power System Frequency Estimation U Sing the Kernel Least Mean Square Algorithm and the Clarke Transform. - Maicon Robe Ferreira; Sérgio Jose Melo de Almeida; Eduardo Antonio Cesar da Costa (NGCAS, 2018)

A Fixed-Point Natural Logarithm Approximation Hardware Design Using Taylor Series. - Miguel R. Weirich; Guilherme Paim; Eduardo A. C. da Costa; Sergio Bampi (NGCAS, 2018)

Exploiting Partial Distortion Elimination in the Sum of Absolute Differences for Energy-Efficient HEVC Integer Motion Estimation. - Brunno Abreu; Gustavo M. Santana; Mateus Grellert; Guilherme Paim; Leandro M. G. Rocha; Eduardo A. C. da Costa; Sergio Bampi (SBCCI, 2018)

Optimization of Single-Stage FFT Architectures Using Multiple Constant Multiplication. - João G. Nizer Rahmeier; Eduardo A. C. da Costa; Alessandro Girardi; Sidinei Ghissoni (SBCCI, 2018)

Exploring Architectural Solutions for an Energy-Efficient Kalman Filter Gain Realization. - Pedro Tauã Lopes Pereira; Guilherme Paim; Patrícia Ücker; Eduardo A. C. da Costa; Sérgio J. M. de Almeida; Sergio Bampi (ICECS, 2019)

A Configurable Pruning Gaussian Image Filter for Energy-Efficient Edge Detection. - Leonardo Bandeira Soares; Eduardo Antônio César da Costa; Sergio Bampi (ICECS, 2019)

Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing. - Vitor G. Lima; Guilherme Paim; Leandro M. G. Rocha; Leomar S. da Rosa Jr.; Felipe S. Marques 001; Eduardo A. C. da Costa; Vinícius V. Camargo; Rafael Soares; Sergio Bampi (ISCAS, 2019)

HEVC Interpolation Filter Architecture Using Hybrid Encoding Arithmetic Operators. - Rafael S. Ferreira; Guilherme Paim; Brunno A. Abreu; Cláudio Machado Diniz; Eduardo A. C. da Costa; Sergio Bampi (MWSCAS, 2019)

Exploring Motion Vector Cost with Partial Distortion Elimination in Sum of Absolute Differences for HEVC Integer Motion Estimation. - Brunno Abreu; Mateus Grellert; Guilherme Paim; Thomas V. Fontanari; Leandro M. G. Rocha; Eduardo A. C. da Costa; Sergio Bampi (NEWCAS, 2019)

Maximizing the Power-Efficiency of the Approximate Pruned Modified Rounded DCT Exploiting Approximate Adder Compressors. - Guilherme Paim; Leandro M. G. Rocha; Eduardo Antônio César da Costa; Sergio Bampi (NEWCAS, 2019)

IIR Filter Architectures with Truncation Error Feedback for ECG Signal Processing. - Gustavo Ott; Eduardo A. C. da Costa; Sérgio J. M. de Almeida; Mateus Beck Fonseca (Circuits Syst. Signal Process., 2019)

Power-, Area-, and Compression-Efficient Eight-Point Approximate 2-D Discrete Tchebichef Transform Hardware Design Combining Truncation Pruning and Efficient Transposition Buffers. - Guilherme Paim; Leandro Mateus Giacomini Rocha; Gustavo Madeira Santana; Leonardo Bandeira Soares; Eduardo Antonio Cesar da Costa; Sergio Bampi (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Design Methodology to Explore Hybrid Approximate Adders for Energy-Efficient Image and Video Processing Accelerators. - Leonardo Bandeira Soares; Morgana Macedo Azevedo da Rosa; Cláudio Machado Diniz; Eduardo Antonio Cesar da Costa; Sergio Bampi (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

An Efficient NLMS-based VLSI Architecture for Robust FECG Extraction and FHR Processing. - Patrícia U. L. da Costa; Guilherme Paim; Leandro M. G. Rocha; Eduardo A. C. da Costa; Sérgio Almeida 001; Sergio Bampi (ICECS, 2020)

The Radix-2m Squared Multiplier. - Morgana M. A. da Rosa; Guilherme Paim; Leandro M. G. Rocha; Eduardo A. C. da Costa; Sergio Bampi (ICECS, 2020)

Exploring Efficient Adder Compressors for Power-Efficient Sum of Squared Differences Design. - Morgana M. A. da Rosa; Guilherme Paim; Leandro M. G. Rocha; Eduardo A. C. da Costa; Sergio Bampi (ICECS, 2020)

Exploring NLMS and IPNLMS Adaptive Filtering VLSI Hardware Architectures for Robust EEG Signal Artifacts Elimination. - Andrei La Rosa; Patrícia Ücker; Guilherme Paim; Eduardo A. C. da Costa; Sérgio J. M. de Almeida; Sergio Bampi (ICECS, 2020)

An Efficient N-bit 8-2 Adder Compressor with a Constant Internal Carry Propagation Delay. - Thomas V. Fontanari; Guilherme Paim; Leandro M. G. Rocha; Patrícia Ücker; Eduardo A. C. da Costa; Sergio Bampi (LASCAS, 2020)

Energy-Efficient Haar Transform Architectures Using Efficient Addition Schemes. - Henrique Seidel; Morgana Macedo Azevedo da Rosa; Guilherme Paim; Eduardo A. C. da Costa; Sérgio J. M. de Almeida; Sergio Bampi (LASCAS, 2020)

Optimizing Iterative-based Dividers for an Efficient Natural Logarithm Operator Design. - Patrícia Ücker; Miguel R. Weirich; Guilherme Paim; Eduardo A. C. da Costa; Sergio Bampi (LASCAS, 2020)

Combining m=2 Multipliers and Adder Compressors for Power Efficient Radix-4 Butterfly. - Guilherme da Costa Ferreira; Leandro M. G. Rocha; Eduardo A. C. da Costa; Sergio Bampi (MWSCAS, 2020)

Optimizing the Montgomery Modular Multiplier for a Power- and Area-Efficient Hardware Architecture. - Mateus Terribele Leme; Guilherme Paim; Leandro M. G. Rocha; Patrícia Ücker; Vitor G. Lima; Rafael Soares; Eduardo A. C. da Costa; Sergio Bampi (MWSCAS, 2020)

Improving the Partial Product Tree Compression on Signed Radix-2m Parallel Multipliers. - Leandro M. G. Rocha; Morgana Macedo; Guilherme Paim; Eduardo A. C. da Costa; Sergio Bampi (NEWCAS, 2020)

Power-Efficient Approximate Newton-Raphson Integer Divider Applied to NLMS Adaptive Filter for High-Quality Interference Cancelling. - Vagner Guidotti; Guilherme Paim; Leandro M. G. Rocha; Eduardo A. C. da Costa; Sérgio J. M. de Almeida; Sergio Bampi (Circuits Syst. Signal Process., 2020)

An Energy-Efficient and Approximate Accelerator Design for Real-Time Canny Edge Detection. - Leonardo Bandeira Soares; Julio F. R. Oliveira; Eduardo Antonio Cesar da Costa; Sergio Bampi (Circuits Syst. Signal Process., 2020)

Exploring high-order adder compressors for power reduction in sum of absolute differences architectures for real-time UHD video encoding. - Guilherme Paim; Gustavo M. Santana; Brunno A. Abreu; Leandro M. G. Rocha; Mateus Grellert; Eduardo A. C. da Costa; Sergio Bampi (J. Real Time Image Process., 2020)

A Cross-Layer Gate-Level-to-Application Co-Simulation for Design Space Exploration of Approximate Circuits in HEVC Video Encoders. - Guilherme Paim; Leandro Mateus Giacomini Rocha; Hussam Amrouch; Eduardo Antônio César da Costa; Sergio Bampi; Jörg Henkel (IEEE Trans. Circuits Syst. Video Technol., 2020)

Sensitivity of FinFET Adders to PVT Variations and Sleep Transistor as a Mitigation Strategy. - Gerson D. Andrade; Ricardo A. L. Reis; Eduardo A. C. da Costa; Alexandra L. Zimpeck (APCCAS, 2021)

Boosting the Efficiency of the Harmonics Elimination VLSI Architecture by Arithmetic Approximations. - Patrícia U. L. da Costa; Pedro Tauã Lopes Pereira; Guilherme Paim; Eduardo A. C. da Costa; Sergio Bampi (ICECS, 2021)

A Power-Efficient FFT Hardware Architecture Exploiting Approximate Adders. - Guilherme da Costa Ferreira; Pedro Tauã Lopes Pereira; Guilherme Paim; Eduardo A. C. da Costa; Sergio Bampi (LASCAS, 2021)

Exploring Approximate Adders for Power-Efficient Harmonics Elimination Hardware Architectures. - Pedro Tauã Lopes Pereira; Guilherme Paim; Guilherme da Costa Ferreira; Eduardo A. C. da Costa; Sérgio Almeida 001; Sergio Bampi (LASCAS, 2021)

Exploring NLMS-Based Adaptive Filter Hardware Architectures for Eliminating Power Line Interference in EEG Signals. - Andrei La Rosa; Pedro Tauã Lopes Pereira; Patrícia Ücker; Guilherme Paim; Eduardo A. C. da Costa; Sergio Bampi; Sérgio Almeida 001 (Circuits Syst. Signal Process., 2021)

Low-power fast Fourier transform hardware architecture combining a split-radix butterfly and efficient adder compressors. - Guilherme da Costa Ferreira; Guilherme Paim; Leandro M. G. Rocha; Gustavo M. Santana; Renato H. Neuenfeld; Eduardo A. C. da Costa; Sergio Bampi (IET Comput. Digit. Tech., 2021)

Fixed-Point NLMS and IPNLMS VLSI Architectures for Accurate FECG and FHR Processing. - Patrícia Ücker Leleu da Costa; Guilherme Paim; Leandro Mateus Giacomini Rocha; Eduardo Antônio César da Costa; Sérgio Jose Melo de Almeida; Sergio Bampi (IEEE Trans. Biomed. Circuits Syst., 2021)

On the Resiliency of NCFET Circuits Against Voltage Over-Scaling. - Guilherme Paim; Georgios Zervakis 001; Girish Pahwa; Yogesh Singh Chauhan; Eduardo Antonio Cesar da Costa; Sergio Bampi; Jörg Henkel; Hussam Amrouch (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy-Efficient ECG Signal Processing. - Henrique Seidel; Morgana Macedo Azevedo da Rosa; Guilherme Paim; Eduardo Antônio César da Costa; Sérgio J. M. de Almeida; Sergio Bampi (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

An Energy-Efficient Haar Wavelet Transform Architecture for Respiratory Signal Processing. - Morgana Macedo Azevedo da Rosa; Henrique Seidel; Guilherme Paim; Eduardo A. C. da Costa; Sérgio J. M. de Almeida; Sergio Bampi (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Architectural Exploration for Energy-Efficient Fixed-Point Kalman Filter VLSI Design. - Pedro Tauã Lopes Pereira; Guilherme Paim; Patrícia Ücker Leleu da Costa; Eduardo Antônio César da Costa; Sérgio Jose Melo de Almeida; Sergio Bampi (IEEE Trans. Very Large Scale Integr. Syst., 2021)

An Efficient Exponential Unit Designed in VLSI CMOS with Custom Operators. - Patrícia U. L. da Costa; Morgana M. A. da Rosa; Guilherme Paim; Eduardo Antonio Cesar da Costa; Rafael Soares; Sergio Bampi (ICECS 2022, 2022)

Exploring Approximate Arithmetic Units for a Power-Efficient Kalman Gain VLSI Design. - Pedro Tauã Lopes Pereira; Guilherme Paim; Eduardo A. C. da Costa; Sérgio J. M. de Almeida; Sergio Bampi (ICECS 2022, 2022)

Discrete Haar Wavelet Transform Hardware Design for Energy-Efficient Image Watermarking. - Morgana Macedo Azevedo da Rosa; Guilherme Paim; Rafael Soares; Eduardo A. C. da Costa; Sergio Bampi (ICECS 2022, 2022)

AxRSU: Approximate Radix-4 Squarer Unit. - Morgana Macedo Azevedo da Rosa; Guilherme Paim; Jorge Castro-Godínez; Eduardo A. C. da Costa; Rafael Iankowski Soares; Sergio Bampi (ISCAS, 2022)

Improved Approximate Multipliers for Single-Precision Floating-Point Hardware Design. - Patrícia U. L. da Costa; Pedro Tauã Lopes Pereira; Brunno A. Abreu; Guilherme Paim; Eduardo A. C. da Costa; Sergio Bampi (LASCAS, 2022)

The 4-2 Fused Adder-Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures. - Bianca Silveira; Guilherme Paim; Brunno Alves Abreu; Rafael dos Santos Ferreira; Cláudio Machado Diniz; Eduardo Antônio César da Costa; Sergio Bampi (Circuits Syst. Signal Process., 2022)

A Framework for Crossing Temperature-Induced Timing Errors Underlying Hardware Accelerators to the Algorithm and Application Layers. - Guilherme Paim; Hussam Amrouch; Leandro M. G. Rocha; Brunno Abreu; Eduardo Antônio César da Costa; Sergio Bampi; Jörg Henkel (IEEE Trans. Computers, 2022)

Energy-Quality Scalable Design Space Exploration of Approximate FFT Hardware Architectures. - Pedro Tauã Lopes Pereira; Patrícia Ücker Leleu da Costa; Guilherme da Costa Ferreira; Brunno Alves de Abreu; Guilherme Paim; Eduardo Antônio César da Costa; Sergio Bampi (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Bridging the Gap Between Voltage Over-Scaling and Joint Hardware Accelerator-Algorithm Closed-Loop. - Guilherme Paim; Hussam Amrouch; Eduardo Antônio César da Costa; Sergio Bampi; Jörg Henkel (IEEE Trans. Circuits Syst. Video Technol., 2022)

AxASRE: A Novel Approach to Approximate Adder Synthesis Results Estimation. - Pedro Tauã Lopes Pereira; Guilherme Paim; Paulo F. Flores; Eduardo A. C. da Costa; Sergio Bampi (DSN-W, 2023)

An Ultra Low-Energy VLSI Approximate Discrete Haar Wavelet Transform for ECG Data Compression. - Arthur Cardozo; Morgana M. A. da Rosa; Rafael Soares; Eduardo Costa 001; Sergio Bampi (ICECS, 2023)

An Optimized VLSI Exponential Unit Design Exploring Efficient Arithmetic Operation Strategies. - Patrícia U. L. da Costa; Morgana M. A. da Rosa; Rafael Soares; Eduardo A. C. da Costa; Sergio Bampi (ICECS, 2023)

New Energy-Efficient 3-2 and 4-2 Approximate Adder Compressors Topologies. - Rodrigo Lopes; Leonardo Antonietti; Morgana M. A. da Rosa; Eduardo Costa 001; Rafael Soares; Sergio Bampi (ICECS, 2023)

Accuracy-, Delay- and Area-Driven Evaluation of Lower-Part Approximate Parallel Prefix Adder. - Morgana M. A. da Rosa; Eduardo Costa 001; Rafael Soares; Sergio Bampi (ICECS, 2023)

An Energy-Efficient StEFCal VLSI Design with Approximate Squarer and Divider Units. - Morgana M. A. da Rosa; Patrícia U. L. da Costa; Guilherme Paim; Eduardo A. C. da Costa; Rafael Soares; Sergio Bampi (LASCAS, 2023)

Architectural Exploration for Energy-Efficient LMS and NLMS Adaptive Filters VLSI Design. - Pedro Tauã Lopes Pereira; Guilherme Paim; Eduardo A. C. da Costa; Paulo F. Flores; Sergio Bampi (NEWCAS, 2023)

Exploring Security Threats by Hardware-Faults in Approximate Arithmetic Computing. - Morgana Macedo Azevedo da Rosa; Eduardo A. C. da Costa; Rafael Iankowski Soares; Sergio Bampi (NEWCAS, 2023)

AxPPA: Approximate Parallel Prefix Adders. - Morgana Macedo Azevedo da Rosa; Guilherme Paim; Patrícia Ücker Leleu da Costa; Eduardo Antonio Cesar da Costa; Rafael Iankowski Soares; Sergio Bampi (IEEE Trans. Very Large Scale Integr. Syst., 2023)

ReAdapt: A Reconfigurable Datapath for Runtime Energy-Quality Scalable Adaptive Filters. - Pedro Tauã Lopes Pereira; Guilherme Paim; Eduardo Antônio César da Costa; Sérgio Jose Melo de Almeida; Sergio Bampi (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Energy-Efficient VLSI Squarer Unit with Optimized Radix-2m Multiplication Logic. - Morgana M. A. da Rosa; Eduardo A. C. da Costa; Leandro Mateus Giacomini Rocha; Guilherme Paim; Sergio Bampi (Circuits Syst. Signal Process., 2023)

Robustness Analysis of 3-2 Adder Compressor Designed in 7-nm FinFET Technology. - Gerson D. Andrade; Matheus Silva; Cínthia Schneider; Guilherme Paim; Sergio Bampi; Eduardo Costa 001; Alexandra L. Zimpeck (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Coding Efficiency and Complexity Analysis of the Geometry-based Point Cloud Encoder. - Cristiano Santos; Leandro Tavares; Eduardo A. C. da Costa; Gustavo Rehbein; Guilherme Corrêa 001; Marcelo Schiavon Porto (LASCAS, 2024)

Evaluating the Resilience of the Approximate Parallel Prefix Adder (AxPPA) Against Hardware Trojan Horse Injection. - Eloisa Barros; Morgana Macedo Azevedo da Rosa; Rodrigo Lopes; Leonardo Antonietti; Eduardo A. C. da Costa; Rafael Soares (SBCCI, 2024)

AxMOD: VLSI Modular Reduction Design Exploring Approximate Arithmetic Units. - Lourenço Mulling; Morgana Macedo Azevedo da Rosa; Rafael Soares; Eduardo A. C. da Costa (SBCCI, 2024)

Exploring Approximate Adders for an Energy-Efficient Pre-Processing Pan-Tompkins Algorithm VLSI Design. - Léo Ribeiro; Morgana Macedo Azevedo da Rosa; Rafael Soares; Eduardo A. C. da Costa (SBCCI, 2024)

VLSI Architectures of Approximate Arithmetic Units Applied to Parallel Sensors Calibration. - Morgana Macedo Azevedo da Rosa; Patrícia Ücker Leleu da Costa; Eduardo Antonio Cesar da Costa; Rafael Iankowski Soares; Sergio Bampi (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

AxRSU-2m: Higher-Order m-Bit Approximate Encoders for Radix-2m Squarer Units. - Morgana M. A. da Rosa; Guilherme Paim; Eduardo A. C. da Costa; Rafael Soares; Sergio Bampi (Circuits Syst. Signal Process., 2024)

MAxPy: A Framework for Bridging Approximate Computing Circuits to Its Applications. - Yuri Arbeletche; Guilherme Paim; Brunno Abreu; Sérgio Almeida 001; Eduardo Costa 001; Paulo F. Flores; Sergio Bampi (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

VLSI Architecture for Energy-Efficient and Accurate Pre-Processing Pan-Tompkins Design. - Léo Ribeiro; Patrícia U. L. da Costa; Guilherme Paim; Eduardo A. C. da Costa; Sérgio Jose Melo de Almeida; Sergio Bampi (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Exploring Discrete Haar Wavelet and Cosine Transforms for Accuracy-and Energy-Quality VLSI Watermarking Systems Design. - Morgana M. A. da Rosa; Eduardo A. C. da Costa; Rafael Soares; Sergio Bampi (Circuits Syst. Signal Process., 2024)

Low-Energy NTT and INTT Architectures for Image Encryption and Decryption. - Eloisa Barros; Leonardo Antonietti; Rodrigo Lopes; Morgana da Rosa; Eduardo A. C. da Costa; Rafael Soares (ISCAS, 2025)

Exploring Approximate Adders for Energy-Efficient Discrete Walsh-Hadamard Transform. - Leonardo Antonietti; Rodrigo Lopes; Morgana M. A. da Rosa; Eloisa Barros; Eduardo A. C. da Costa; Rafael Soares (LASCAS, 2025)

Exploring Approximate Adders for Accuracy- and Energy-Quality VLSI Watermarking Systems Design. - Morgana da Rosa; Eduardo Antonio Cesar da Costa; Rafael Soares (LASCAS, 2025)

A Low-Power Level-2 Discrete Haar Wavelet Transform with Approximate Adders for ECG Signal. - Henrique Seidel; Morgana M. A. da Rosa; Rodrigo Lopes; Eduardo A. C. da Costa; Rafael Soares (LASCAS, 2025)

ReAdapt-II: Energy-Quality Optimizations for VLSI Adaptive Filters Through Automatic Reconfiguration and Built-In Iterative Dividers. - Pedro Tauã Lopes Pereira; Patrícia Ücker Leleu da Costa; Eduardo A. C. da Costa; Paulo F. Flores; Sergio Bampi (IEEE Trans. Very Large Scale Integr. Syst., 2025)

RCU- 2m: A VLSI Radix- 2m Cubic Unit. - Eduardo Antonio Cesar da Costa; Morgana Macedo Azevedo da Rosa (IEEE Trans. Very Large Scale Integr. Syst., 2025)

FALSAx: An Integrated Framework for Accuracy and Logic Synthesis Estimation of Approximate Adders. - Morgana Macedo Azevedo da Rosa; Leonardo Antonietti; Rodrigo Lopes; Eloisa Barros; Eduardo Antonio Cesar da Costa; Rafael Soares (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Efficiency and complexity analysis of video-based and geometry-based point cloud encoders. - Cristiano Santos; Gustavo Rehbein; Eduardo A. C. da Costa; Guilherme Corrêa 001; Marcelo Schiavon Porto (J. Real Time Image Process., 2025)

Energy-efficient discrete Haar Wavelet Transform architectures exploring approximate adders for high-quality image compression and reconstruction. - Carlos Eduardo Reis Urban; Morgana Macedo Azevedo da Rosa; Eduardo Antonio Cesar da Costa (Future Gener. Comput. Syst., 2026)