A dynamic communication strategy for the distributed ATPG system DPLATON. - Maria José Aguado; Miguel Miranda; Eduardo de la Torre; Carlos A. López-Barrio (EURO-DAC, 1993)

Distributed Implementation of an ATPG System Using Dynamic Fault Allocation. - Maria José Aguado; Eduardo de la Torre; Miguel Miranda; Carlos A. López-Barrio (ITC, 1993)

Model generation of test logic for macrocell based designs. - Eduardo de la Torre; J. Calvo; Javier Uceda (EURO-DAC, 1996)

Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models. - Teresa Riesgo; Yago Torroja; Eduardo de la Torre; Javier Uceda (DATE, 1998)

Design methodologies based on hardware description languages. - Teresa Riesgo; Yago Torroja; Eduardo de la Torre (IEEE Trans. Ind. Electron., 1999)

Highly Configurable Control Boards: A Tool and a Design Experience. - Eduardo de la Torre; Teresa Riesgo; Javier Uceda; E. Macip; M. Rizzi (IEEE International Workshop on Rapid System Prototyping, 2000)

Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion. - Mario García-Valderas; Eduardo de la Torre; F. Ariza; Teresa Riesgo (FPL, 2004)

Flexible Core Reallocation for Virtex II Structures. - Yana Esteves Krasteva; Ana B. Jimeno; Eduardo de la Torre; Teresa Riesgo (ERSA, 2005)

Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs. - Yana Esteves Krasteva; Ana B. Jimeno; Eduardo de la Torre; Teresa Riesgo (IEEE International Workshop on Rapid System Prototyping, 2005)

Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems. - Yana Esteves Krasteva; Eduardo de la Torre; Teresa Riesgo; Didier Joly (FPL, 2006)

Partial Reconfiguration for Core Reallocation and Flexible Communications. - Yana Esteves Krasteva; Eduardo de la Torre; Teresa Riesgo (ReCoSoC, 2006)

A Modular Architecture for Nodes in Wireless Sensor Networks. - Jorge Portilla; Angel de Castro; Eduardo de la Torre; Teresa Riesgo (J. Univers. Comput. Sci., 2006)

Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management. - Yana Esteves Krasteva; Eduardo de la Torre; Teresa Riesgo (ISCAS, 2007)

A digital system to emulate wireless networks. - Eduardo Peña; Eduardo de la Torre; Angel de Castro; Teresa Riesgo (IET Comput. Digit. Tech., 2007)

A Fast Emulation-Based NoC Prototyping Framework. - Yana Esteves Krasteva; Francisco Criado; Eduardo de la Torre; Teresa Riesgo (ReConFig, 2008)

Generic Systolic Array for Run-Time Scalable Cores. - Andrés Otero; Yana Esteves Krasteva; Eduardo de la Torre; Teresa Riesgo (ARC, 2010)

A Modular Peripheral to Support Self-Reconfiguration in SoCs. - Andrés Otero; Angel Morales-Cas; Jorge Portilla; Eduardo de la Torre; Teresa Riesgo (DSD, 2010)

Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. - Andrés Otero; Eduardo de la Torre; Teresa Riesgo; Yana Esteves Krasteva (FPL, 2010)

Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors. - Jorge Portilla; Andrés Otero; Eduardo de la Torre; Teresa Riesgo; Oliver Stecklina; Steffen Peter; Peter Langendörfer (Int. J. Distributed Sens. Networks, 2010)

Reconfigurable Networks on Chip: DRNoC architecture. - Yana Esteves Krasteva; Eduardo de la Torre; Teresa Riesgo (J. Syst. Archit., 2010)

A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems. - Andrés Otero; Rubén Salvador; Javier Mora 001; Eduardo de la Torre; Teresa Riesgo; Lukás Sekanina (AHS, 2011)

Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support. - Rubén Salvador; Andrés Otero; Javier Mora 001; Eduardo de la Torre; Teresa Riesgo; Lukás Sekanina (AHS, 2011)

Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs. - Andrés Otero; Eduardo de la Torre; Teresa Riesgo; Teresa Cervero; Sebastián López; Gustavo M. Callicó; Roberto Sarmiento (FPL, 2011)

A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs. - Teresa Cervero; Andrés Otero; Sebastián López; Eduardo de la Torre; Gustavo M. Callicó; Roberto Sarmiento; Teresa Riesgo (ICME, 2011)

A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations. - Wei He 015; Eduardo de la Torre; Teresa Riesgo (ReConFig, 2011)

Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems. - Rubén Salvador; Andrés Otero; Javier Mora 001; Eduardo de la Torre; Lukás Sekanina; Teresa Riesgo (ReConFig, 2011)

An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation. - Wei He 015; Eduardo de la Torre; Teresa Riesgo (COSADE, 2012)

FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels. - Iakovos Mavroidis; Ioannis Mavroidis; Ioannis Papaefstathiou; Luciano Lavagno; Mihai T. Lazarescu; Eduardo de la Torre; Florian Schäfer 001 (DSD, 2012)

Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. - Rubén Salvador; Andrés Otero; Javier Mora 001; Eduardo de la Torre; Teresa Riesgo; Lukás Sekanina (FPL, 2012)

Automatic generation of identical routing pairs for FPGA implemented DPL logic. - Wei He 015; Andrés Otero; Eduardo de la Torre; Teresa Riesgo (ReConFig, 2012)

Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems. - Andrés Otero; Eduardo de la Torre; Teresa Riesgo (ReConFig, 2012)

Power management techniques in an FPGA-based WSN node for high performance applications. - Miguel Lombardo; Julio Camarero; Juan Valverde; Jorge Portilla; Eduardo de la Torre; Teresa Riesgo (ReCoSoC, 2012)

Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks. - Juan Valverde; Andrés Otero; Miguel Lopez; Jorge Portilla; Eduardo de la Torre; Teresa Riesgo (Sensors, 2012)

A noise-agnostic self-adaptive image processing application based on evolvable hardware. - Javier Mora 001; Angel Gallego; Andrés Otero; Blanca López; Eduardo de la Torre; Teresa Riesgo (DASIP, 2013)

Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform. - Javier Mora 001; Angel Gallego; Andrés Otero; Eduardo de la Torre; Teresa Riesgo (DASIP, 2013)

A self-adaptive image processing application based on evolvable and scalable hardware. - Angel Gallego; Javier Mora 001; Andrés Otero; Blanca López; Eduardo de la Torre; Teresa Riesgo (FPL, 2013)

A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays. - Angel Gallego; Javier Mora 001; Andrés Otero; Rubén Salvador; Eduardo de la Torre; Teresa Riesgo (IPDPS Workshops, 2013)

A scalable evolvable hardware processing array. - Angel Gallego; Javier Mora 001; Andrés Otero; Eduardo de la Torre; Teresa Riesgo (ReConFig, 2013)

Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing. - Rubén Salvador; Andrés Otero; Javier Mora 001; Eduardo de la Torre; Teresa Riesgo; Lukás Sekanina (IEEE Trans. Computers, 2013)

Power-aware multi-objective evolvable hardware system on an FPGA. - Blanca López; Juan Valverde; Eduardo de la Torre; Teresa Riesgo (AHS, 2014)

A run time adaptive architecture to trade-off performance for fault tolerance applied to a DVB on-board processor. - Filip Veljkovic; Teresa Riesgo; Eduardo de la Torre; Raul Regada; Luis Berrojo (AHS, 2014)

A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems. - Juan Valverde; Alfonso Rodríguez 002; Julio Camarero; Andrés Otero; Jorge Portilla; Eduardo de la Torre; Teresa Riesgo (FPL, 2014)

A Progressive Dual-Rail Routing Repair Approach for FPGA Implementation of Crypto Algorithm. - Chenyang Tu; Wei He; Neng Gao; Eduardo de la Torre; Zeyi Liu; Limin Liu (ISPEC, 2014)

Dynamic management of multikernel multithread accelerators using Dynamic Partial Reconfiguration. - Alfonso Rodríguez 002; Juan Valverde; Eduardo de la Torre; Teresa Riesgo (ReCoSoC, 2014)

Introduction to the special issue on FPGA Technology and Applications. - Peter Athanas; René Cumplido; Eduardo de la Torre (Comput. Electr. Eng., 2014)

Introduction to Special issue on FPGA Devices and Applications. - Peter M. Athanas; René Cumplido; Claudia Feregrino Uribe; Eduardo de la Torre (Microprocess. Microsystems, 2014)

Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic. - Wei He 015; Andrés Otero; Eduardo de la Torre; Teresa Riesgo (Microprocess. Microsystems, 2014)

Adaptive reconfigurable voting for enhanced reliability in medium-grained fault tolerant architectures. - Filip Veljkovic; Teresa Riesgo; Eduardo de la Torre (AHS, 2015)

Live demonstration: A dynamically adaptable image processing application running in an FPGA-based WSN platform. - Alfonso Rodríguez 002; Juan Valverde; Cesar Castanares; Jorge Portilla; Eduardo de la Torre; Teresa Riesgo (ISCAS, 2015)

Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs. - Alfonso Rodríguez 002; Juan Valverde; Eduardo de la Torre (ReConFig, 2015)

Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs. - Javier Mora 001; Andrés Otero; Eduardo de la Torre; Teresa Riesgo (ReCoSoC, 2015)

Message from the chairs. - Alberto García Ortiz; Daniel Gregorek; Eduardo de la Torre; Juha Plosila (ReCoSoC, 2015)

Execution modeling in self-aware FPGA-based architectures for efficient resource management. - Alfonso Rodríguez 002; Juan Valverde; Cesar Castanares; Jorge Portilla; Eduardo de la Torre; Teresa Riesgo (ReCoSoC, 2015)

Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis. - Wei He 015; Shivam Bhasin; Andrés Otero; Tarik Graba; Eduardo de la Torre; Jean-Luc Danger (IET Inf. Secur., 2015)

Introduction to Special issue on Reconfigurable computing and FPGAs. - René Cumplido; Eduardo de la Torre; Claudia Feregrino Uribe; Michael J. Wirthlin (Microprocess. Microsystems, 2015)

Letter from the guest editors of the special issue on DCIS 2014. - Eduardo de la Torre; Jorge Portilla; Teresa Riesgo (Microprocess. Microsystems, 2015)

Introduction to the Special Section on FPGAs Technology and Applications. - René Cumplido; Peter Athanas; Eduardo de la Torre (Comput. Electr. Eng., 2016)

A scalable H.264/AVC deblocking filter architecture. - Teresa Cervero; Andrés Otero; Sebastián López; Eduardo de la Torre; Gustavo M. Callicó; Teresa Riesgo; Roberto Sarmiento (J. Real Time Image Process., 2016)

Dynamic reconfiguration under RTEMS for fault mitigation and functional adaptation in SRAM-based SoPCs for space systems. - Arturo Perez; Leonardo Suriano; Andrés Otero; Eduardo de la Torre (AHS, 2017)

Cross-layer design of reconfigurable cyber-physical systems. - Michael Masin; Francesca Palumbo; Hans Myrhaug; J. A. de Oliveira Filho; M. Pastena; Maxime Pelcat; Luigi Raffo; Francesco Regazzoni 001; A. A. Sanchez; Antonella Toffetti; Eduardo de la Torre; Katiuscia Zedda (DATE, 2017)

Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoC. - Leonardo Suriano; Alfonso Rodríguez 002; Karol Desnos; Maxime Pelcat; Eduardo de la Torre (ReCoSoC, 2017)

Performance Analysis of SEE Mitigation Techniques on Zynq Ultrascale + Hardened Processing Fabrics. - Arturo Perez; Andrés Otero; Eduardo de la Torre (AHS, 2018)

Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems. - Tiziana Fanni; Alfonso Rodríguez 002; Carlo Sau; Leonardo Suriano; Francesca Palumbo; Luigi Raffo; Eduardo de la Torre (ReConFig, 2018)

IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado. - Rafael Zamacola; Alberto García-Martínez; Javier Mora 001; Andrés Otero; Eduardo de la Torre (ReConFig, 2018)

A Unified Hardware/Software Monitoring Method for Reconfigurable Computing Architectures Using PAPI. - Leonardo Suriano; Daniel Madroñal; Alfonso Rodríguez 002; Eduardo Juárez 001; César Sanz; Eduardo de la Torre (ReCoSoC, 2018)

Accelerating the evolution of a systolic array-based evolvable hardware system. - Javier Mora 001; Eduardo de la Torre (Microprocess. Microsystems, 2018)

A Runtime-Scalable and Hardware-Accelerated Approach to On-Board Linear Unmixing of Hyperspectral Images. - Alberto García Ortiz; Alfonso Rodríguez 002; Raúl Guerra; Sebastián López; Andrés Otero; Roberto Sarmiento; Eduardo de la Torre (Remote. Sens., 2018)

FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework. - Alfonso Rodríguez 002; Juan Valverde; Jorge Portilla; Andrés Otero; Teresa Riesgo; Eduardo de la Torre (Sensors, 2018)

A Dataflow Implementation of Inverse Kinematics on Reconfigurable Heterogeneous MPSoC. - Luca Fanni; Leonardo Suriano; Claudio Rubattu; Pablo Sánchez; Eduardo de la Torre; Francesca Palumbo (CPS Summer School, PhD Workshop, 2019)

Hardware Accelerator for Ethanol Detection in Water Media based on Machine Learning Techniques. - Rodrigo Marino; Sergio Quintero; José Manuel Lanza-Gutiérrez; Teresa Riesgo; Miguel Holgado; Jorge Portilla; Eduardo de la Torre (DCIS, 2019)

Artificial Vision on Edge IoT Devices: A Practical Case for 3D Data Classification. - Cristian Wisultschew; Andrés Otero; Jorge Portilla; Eduardo de la Torre (DCIS, 2019)

Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems. - Rafael Zamacola; Alberto García-Martínez; Javier Mora 001; Andrés Otero; Eduardo de la Torre (FCCM, 2019)

Data Transfer Modeling and Optimization in Reconfigurable Multi-Accelerator Systems. - Alberto García Ortiz; Alfonso Rodríguez 002; Andrés Otero; Eduardo de la Torre (ReCoSoC, 2019)

Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach. - Francesca Palumbo; Tiziana Fanni; Carlo Sau; Alfonso Rodríguez 002; Daniel Madroñal; Karol Desnos; Antoine Morvan; Maxime Pelcat; Claudio Rubattu; Raquel Lazcano; Luigi Raffo; Eduardo de la Torre; et al. (SAMOS, 2019)

Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression. - Alfonso Rodríguez 002; Lucana Santos; Roberto Sarmiento; Eduardo de la Torre (IEEE Access, 2019)

On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming. - Javier Mora 001; Rubén Salvador; Eduardo de la Torre (Genet. Program. Evolvable Mach., 2019)

DAMHSE: Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototyping. - Leonardo Suriano; Florian Arrestier; Alfonso Rodríguez 002; Julien Heulot; Karol Desnos; Maxime Pelcat; Eduardo de la Torre (Microprocess. Microsystems, 2019)

Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems. - Alberto García Ortiz; Rafael Zamacola; Alfonso Rodríguez 002; Andrés Otero; Eduardo de la Torre (ARC, 2020)

Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs. - Leonardo Suriano; David Lima; Eduardo de la Torre (ARC, 2020)

Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation. - Arturo Perez; Alfonso Rodríguez 002; Andrés Otero; David González Arjona; Álvaro Jiménez-Peralo; Miguel Ángel Verdugo; Eduardo de la Torre (IEEE Access, 2020)

Exploiting Multi-Level Parallelism for Run-Time Adaptive Inverse Kinematics on Heterogeneous MPSoCs. - Leonardo Suriano; Andrés Otero; Alfonso Rodríguez 002; Manuel Sánchez-Renedo; Eduardo de la Torre (IEEE Access, 2020)

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems. - Rafael Zamacola; Andrés Otero; Alberto García-Martínez; Eduardo de la Torre (IEEE Access, 2020)

Run-Time Monitoring and ML-Based Modeling in Reconfigurable Multi-Accelerator Systems. - Juan Encinas; Alfonso Rodríguez 002; Andrés Otero; Eduardo de la Torre (DCIS, 2021)

A Machine-Learning-Based Distributed System for Fault Diagnosis With Scalable Detection Quality in Industrial IoT. - Rodrigo Marino; Cristian Wisultschew; Andrés Otero; José Manuel Lanza-Gutiérrez; Jorge Portilla; Eduardo de la Torre (IEEE Internet Things J., 2021)

Multi-grain reconfigurable and scalable overlays for hardware accelerator composition. - Rafael Zamacola; Andrés Otero; Eduardo de la Torre (J. Syst. Archit., 2021)

A Multi-FPGA Scalable Framework for Deep Reinforcement Learning Through Neuroevolution. - Javier Laserna; Andrés Otero; Eduardo de la Torre (ARC, 2022)

Extending RISC-V Processor Datapaths with Multi-Grain Reconfigurable Overlays. - Daniel Vázquez; Alfonso Rodríguez 002; Andrés Otero; Eduardo de la Torre (DCIS, 2022)

Just-In-Time Composition of Reconfigurable Overlays (Invited Talk). - Rafael Zamacola; Andrés Otero; Alfonso Rodríguez 002; Eduardo de la Torre (PARMA-DITAM@HiPEAC, 2022)

Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. - Alfonso Rodríguez 002; Andrés Otero; Marco Platzner; Eduardo de la Torre (IEEE Trans. Computers, 2022)

Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning. - Andrés Otero; Guillermo Sanllorente; Eduardo de la Torre; José L. Núñez-Yáñez (ARC, 2023)

Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite. - José L. Núñez-Yáñez; J. Andrés Otero; Eduardo de la Torre (Microprocess. Microsystems, 2023)

Data-driven modeling of reconfigurable multi-accelerator systems under dynamic workloads. - Juan Encinas; Alfonso Rodríguez 002; Andrés Otero; Eduardo de la Torre (Microprocess. Microsystems, 2024)