Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology. - Reda Boumchedda; Jean-Philippe Noel; Bastien Giraud; Adam Makosiej; Marco Antonio Rios; Eduardo Esmanhotto; Emilien Bourde-Cicé; Mathis Bellet; David Turgis; Edith Beigné (NANOARCH, 2018)

Ex Situ Transfer of Bayesian Neural Networks to Resistive Memory-Based Inference Hardware. - Thomas Dalgaty; Eduardo Esmanhotto; Niccolo Castellani; Damien Querlioz; Elisa Vianello (Adv. Intell. Syst., 2021)

A novel 3D 1T1R RRAM architecture for memory-centric Hyperdimensional Computing. - T. Dubreuil; P. Amari; Sylvain Barraud; Joris Lacord; Eduardo Esmanhotto; Valentina Meli; S. Martin; Niccolo Castellani; Bernard Previtali; François Andrieu (IMW, 2022)

Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations. - Eduardo Esmanhotto; Tifenn Hirtzlin; Niccolo Castellani; S. Martin; Bastien Giraud; François Andrieu; Jean-François Nodin; Damien Querlioz; Jean-Michel Portal; Elisa Vianello (IRPS, 2022)

Hardware calibrated learning to compensate heterogeneity in analog RRAM-based Spiking Neural Networks. - Filippo Moro; Eduardo Esmanhotto; Tifenn Hirtzlin; Niccolo Castellani; Ahmed Trabelsi; Thomas Dalgaty; Gabriel Molas; François Andrieu; Stefano Brivio; Sabina Spiga; Giacomo Indiveri; Melika Payvand; et al. (ISCAS, 2022)

Experimental Demonstration of Multilevel Resistive Random Access Memory Programming for up to Two Months Stable Neural Networks Inference Accuracy. - Eduardo Esmanhotto; Tifenn Hirtzlin; Djohan Bonnet; Niccolo Castellani; Jean-Michel Portal; Damien Querlioz; Elisa Vianello (Adv. Intell. Syst., 2022)