Eduardo Henrique Molina da Cruz

Arthur Francisco Lorenzon

Antonio C. S. Beck

Concurr. Comput. Pract. Exp., 2023

2021

Online Thread and Data Mapping Using a Sharing-Aware Memory Management Unit.

[BibT_eX]

[DOI]

ACM Trans. Model. Perform. Evaluation Comput. Syst., 2021

Energy efficiency and portability of oil and gas simulations on multicore and graphics processing unit architectures.

[BibT_eX]

[DOI]

Alexandre S. Carissimi

Concurr. Comput. Pract. Exp., 2021

2019

EagerMap: A Task Mapping Algorithm to Improve Communication and Load Balancing in Clusters of Multicore Systems.

[BibT_eX]

[DOI]

ACM Trans. Parallel Comput., 2019

Optimization strategies for geophysics models on manycore systems.

[BibT_eX]

[DOI]

Int. J. High Perform. Comput. Appl., 2019

Memory Performance and Bottlenecks in Multicore and GPU Architectures.

[BibT_eX]

[DOI]

Francis B. Moreira

Dalvan Griebler

Luiz Gustavo Fernandes

Proceedings of the 27th Euromicro International Conference on Parallel, 2019

2018

Thread and Data Mapping for Multicore Systems - Improving Communication and Memory Accesses

[BibT_eX]

[DOI]

Springer Briefs in Computer Science, Springer, ISBN: 978-3-319-91073-4, 2018

Optimizing Geophysics Models Using Thread and Data Mapping.

[BibT_eX]

[DOI]

Jairo Panetta

Proceedings of the Symposium on High Performance Computing Systems, 2018

Improving Oil and Gas Simulation Performance Using Thread and Data Mapping.

[BibT_eX]

[DOI]

Alexandre S. Carissimi

Proceedings of the High Performance Computing Systems - 19th Symposium, 2018

Optimizing Machine Learning Algorithms on Multi-Core and Many-Core Architectures Using Thread and Data Mapping.

[BibT_eX]

[DOI]

Arthur M. Krause

Marcelo Pasin

Pascal Felber

Proceedings of the 26th Euromicro International Conference on Parallel, 2018

Improving Communication and Load Balancing with Thread Mapping in Manycore Systems.

[BibT_eX]

[DOI]

Israel Koren

Proceedings of the 26th Euromicro International Conference on Parallel, 2018

2017

Modeling memory access behavior for data mapping.

[BibT_eX]

[DOI]

Int. J. High Perform. Comput. Appl., 2017

Affinity-Based Thread and Data Mapping in Shared Memory Systems.

[BibT_eX]

[DOI]

Israel Koren

ACM Comput. Surv., 2017

Strategies to Improve the Performance of a Geophysics Model for Different Manycore Systems.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Symposium on Computer Architecture and High Performance Computing Workshops, 2017

Optimizing memory affinity with a hybrid compiler/OS approach.

[BibT_eX]

[DOI]

Proceedings of the Computing Frontiers Conference, 2017

2016

Mapeamento dinâmico de threads e dados usando a unidade de gerência de memória.

[BibT_eX]

[DOI]

PhD thesis, 2016

Kernel-Based Thread and Data Mapping for Improved Memory Affinity.

[BibT_eX]

[DOI]

Anselm Busse

Hans-Ulrich Heiss

IEEE Trans. Parallel Distributed Syst., 2016

Hardware-Assisted Thread and Data Mapping in Hierarchical Multicore Architectures.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2016

LAPT: A locality-aware page table for thread and data mapping.

[BibT_eX]

[DOI]

Parallel Comput., 2016

Communication in Shared Memory: Concepts, Definitions, and Efficient Detection.

[BibT_eX]

[DOI]

Proceedings of the 24th Euromicro International Conference on Parallel, 2016

System energy analysis for shared memory multiprocessing applications.

[BibT_eX]

[DOI]

Dieison Soares Silveira

Sergio Bampi

Gabriel B. Moro

Lucas Mello Schnorr

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

A Sharing-Aware Memory Management Unit for Online Mapping in Multi-core Architectures.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2016: Parallel Processing, 2016

Automatic Communication Optimization of Parallel Applications in Public Clouds.

[BibT_eX]

[DOI]

Emmanuell D. Carreño

Proceedings of the IEEE/ACM 16th International Symposium on Cluster, 2016

2015

Characterizing communication and page usage of parallel applications for thread and data mapping.

[BibT_eX]

[DOI]

Fabrice Dupros

Perform. Evaluation, 2015

Communication-aware process and thread mapping using online communication detection.

[BibT_eX]

[DOI]

Anselm Busse

Hans-Ulrich Heiß

Parallel Comput., 2015

Communication-aware thread mapping using the translation lookaside buffer.

[BibT_eX]

[DOI]

Concurr. Comput. Pract. Exp., 2015

Locality vs. Balance: Exploring Data Mapping Policies on NUMA Systems.

[BibT_eX]

[DOI]

Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

An Efficient Algorithm for Communication-Based Task Mapping.

[BibT_eX]

[DOI]

Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Locality and Balance for Communication-Aware Thread Mapping in Multicore Systems.

[BibT_eX]

[DOI]

Mohammad S. Alhakeem

Hans-Ulrich Heiß

Proceedings of the Euro-Par 2015: Parallel Processing, 2015

2014

Dynamic thread mapping of shared memory applications by exploiting cache coherence protocols.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2014

Optimizing Memory Locality Using a Locality-Aware Page Table.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

kMAF: automatic kernel-level management of thread and data affinity.

[BibT_eX]

[DOI]

Anselm Busse

Hans-Ulrich Heiß

Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013

Communication-Based Mapping Using Shared Pages.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Symposium on Parallel and Distributed Processing, 2013

2012

Memory-aware Thread and Data Mapping for Hierarchical Multi-core Platforms.

[BibT_eX]

[DOI]

Marco Antonio Zanata Alves

Alexandre Carissimi

Christiane Pousa Ribeiro

Jean-François Méhaut

Int. J. Netw. Comput., 2012

Using the Translation Lookaside Buffer to Map Threads in Parallel Applications Based on Shared Memory.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

2011

Using Memory Access Traces to Map Threads and Data on Hierarchical Multi-core Platforms.

[BibT_eX]

[DOI]

Marco Antonio Zanata Alves

Alexandre Carissimi