Statistical behavioral modeling and characterization of A/D converters. - Eduardo J. Peralías; Adoración Rueda; José Luis Huertas (ICCAD, 1995)

SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems. - Salvador Mir; Adoración Rueda; Thomas Olbrich; Eduardo J. Peralías; José Luis Huertas (DAC, 1997)

A DFT Technique for Analog-to-Digital Converters with digital correction. - Eduardo J. Peralías; Adoración Rueda; José L. Huertas (VTS, 1997)

An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits. - Juan A. Prieto; Adoración Rueda; Ian Andrew Grout; Eduardo J. Peralías; José L. Huertas; Andrew Mark David Richardson (DATE, 1998)

CMOS pipelined A/D converters with concurrent error detection capability. - Eduardo J. Peralías; Adoración Rueda; José L. Huertas (ICECS, 1998)

DfT and on-line test of high-performance data converters: a practical case. - Eduardo J. Peralías; Adoración Rueda; Juan A. Prieto; José L. Huertas (ITC, 1998)

A high-Q bandpass fully differential SC filter with enhanced testability. - Diego Vázquez; Adoración Rueda; José Luis Huertas; Eduardo J. Peralías (IEEE J. Solid State Circuits, 1998)

A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters. - Eduardo J. Peralías; Antonio J. Acosta 001; Adoración Rueda; José L. Huertas (DATE, 2000)

VHDL-based behavioural description of pipeline ADCs. - Eduardo J. Peralías; Antonio J. Acosta 001; Adoración Rueda; José L. Huertas (ISCAS, 2000)

Alternative DFT Strategies for High-Speed Pipelined Data Converters. - Eduardo J. Peralías; Adoración Rueda; José L. Huertas (LATW, 2000)

An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits. - Raúl Jiménez; Antonio J. Acosta 001; Eduardo J. Peralías; Adoración Rueda (PATMOS, 2000)

Analog/mixed-signal IP modeling for design reuse. - Natividad Martínez Madrid; Eduardo J. Peralías; Antonio J. Acosta 001; Adoración Rueda (DATE, 2001)

Structural testing of pipelined analog to digital converters. - Eduardo J. Peralías; Adoración Rueda; José L. Huertas (ISCAS (1), 2001)

Self-Testable Pipelined ADC with Low Hardware Overhead. - Eduardo J. Peralías; Gloria Huertas; Adoración Rueda; José L. Huertas (VTS, 2001)

New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters. - Eduardo J. Peralías; Adoración Rueda; José Luis Huertas (J. Electron. Test., 2001)

A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda; Ralf Seepold; Natividad Martínez Madrid (DATE, 2002)

Practical Oscillation-Based Test of Integrated Filters. - Gloria Huertas; Diego Vázquez; Eduardo J. Peralías; Adoración Rueda; José Luis Huertas (IEEE Des. Test Comput., 2002)

Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell. - Gloria Huertas; Diego Vázquez; Eduardo J. Peralías; Adoración Rueda; José Luis Huertas (IEEE Des. Test Comput., 2002)

Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (SBCCI, 2003)

Digital Background Gain Error Correction in Pipeline ADCs. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (DATE, 2004)

Impact of random channel mismatch on the SNR and SFDR of time-interleaved ADCs. - Gildas Léger; Eduardo J. Peralías; Adoración Rueda; José Luis Huertas (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

Digital self-tuning technique for continuous-time filters. - Guillermo Zatorre-Navarro; Eduardo J. Peralías; Santiago Celma Pueyo; Concepción Aldea Chagoyen; Nicolás J. Medrano-Marqués (ICECS, 2005)

Full calibration digital techniques for pipeline ADCs. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (ISCAS (3), 2005)

Statistical analysis of a background correlation-based technique for full calibration of pipeline ADCs. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (ISCAS, 2006)

Improved Background Algorithms for Pipeline ADC Full Calibration. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (ISCAS, 2007)

Novel swapping technique for background calibration of capacitor mismatching in pipeline ADCS. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (SBCCI, 2007)

A 1.2V 5.14mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4GHz ZigBee applications. - Antonio Jose Ginés; Ricardo Doldán; Alberto Villegas; Antonio J. Acosta 001; Maria Angeles Jalón; Diego Vázquez; Adoración Rueda; Eduardo J. Peralías (APCCAS, 2008)

A 5GHz wide tuning range LC-VCO in sub-micrometer CMOS technology. - Ricardo Doldán Lorenzo; Antonio Jose Ginés Arteaga; Adoración Rueda; Eduardo J. Peralías (APCCAS, 2008)

A 2.4GHz LNA in a 90-nm CMOS technology designed with ACM model. - Rafaella Fiorelli; Fernando Silveira; Eduardo J. Peralías; Diego Vázquez; Adoración Rueda; José Luis Huertas (SBCCI, 2008)

Simple Evaluation of the Nonlinearity Signature of an ADC Using a Spectral Approach. - Eduardo J. Peralías; Maria Angeles Jalón; Adoración Rueda (VLSI Design, 2008)

On-line estimation of the integral non-linear errors in analogue-to-digital converters without histogram evaluation. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (ECCTD, 2009)

A survey on digital background calibration of ADCs. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (ECCTD, 2009)

Phase noise - consumption trade-off in low power RF-LC-VCO design in micro and nanometric technologies. - Rafaella Fiorelli; Fernando Silveira; Eduardo J. Peralías (SBCCI, 2009)

A fully differential monolithic 2.4GHZ PA for IEEE 802.15.4 based on efficiency design flow. - Rafaella Fiorelli; Eduardo J. Peralías; Nicolás Barabino; Fernando Silveira (ICECS, 2010)

Power optimization of CMOS programmable gain amplifiers with high dynamic range and common-mode feed-forward circuit. - Antonio J. Ginés; Ricardo Doldán; Adoración Rueda; Eduardo J. Peralías (ICECS, 2010)

On-chip biased voltage-controlled oscillator with temperature compensation of the oscillation amplitude for robust I/Q generation. - Antonio J. Ginés; Ricardo Doldán; Manuel J. Barragan Asian; Adoración Rueda; Eduardo J. Peralías (ISCAS, 2010)

ADC Non-Linearity Low-Cost Test Through a Simplified Double-Histogram Method. - Maria Angeles Jalón; Eduardo J. Peralías (J. Electron. Test., 2010)

On Chopper Effects in Discrete-Time SigmaDelta Modulators. - Gildas Léger; Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

2.4-GHz single-ended input low-power low-voltage active front-end for ZigBee applications in 90 nm CMOS. - Rafaella Fiorelli; Alberto Villegas; Eduardo J. Peralías; Diego Vázquez; Adoración Rueda (ECCTD, 2011)

A 3.6mW @ 1.2V high linear 8th-order CMOS complex filter for IEEE 802.15.4 standard. - Alberto Villegas; Diego Vázquez; Eduardo J. Peralías; Adoración Rueda (ESSCIRC, 2011)

Blind Adaptive Estimation of Integral Nonlinear Errors in ADCs Using Arbitrary Input Stimulus. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (IEEE Trans. Instrum. Meas., 2011)

Self-biased input common-mode generation for improving dynamic range and yield in inverter-based filters. - Antonio Jose Ginés; Alberto Villegas; Eduardo J. Peralías; Adoración Rueda (ICECS, 2012)

Analysis of steady-state common-mode response in differential LC-VCOs. - Ricardo Doldán; Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (ISCAS, 2012)

INL systematic reduced-test technique for Pipeline ADCs. - Eduardo J. Peralías; Antonio Jose Ginés; Adoración Rueda (ETS, 2014)

Closed-loop simulation method for evaluation of static offset in discrete-time comparators. - Antonio J. Ginés; Eduardo J. Peralías; Gildas Léger; Adoración Rueda (ICECS, 2014)

An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs. - Juan Núñez 002; Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (LASCAS, 2015)

Background Digital Calibration of Comparator Offsets in Pipeline ADCs. - Antonio Jose Ginés; Eduardo J. Peralías; Adoración Rueda (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator. - Antonio J. Ginés; Eduardo J. Peralías; Gildas Léger; Adoración Rueda; Guillaume Renaud; Manuel J. Barragán; Salvador Mir (ETS, 2016)

Semi-empirical RF MOST model for CMOS 65 nm technologies: Theory, extraction method and validation. - Rafaella Fiorelli; Eduardo J. Peralías (Integr., 2016)

On the limits of machine learning-based test: A calibrated mixed-signal system case study. - Manuel J. Barragán; Gildas Léger; Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (DATE, 2017)

Black-Box Calibration for ADCs With Hard Nonlinear Errors Using a Novel INL-Based Additive Code: A Pipeline ADC Case Study. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Fast Background Calibration of Sampling Timing Skew in SHA-Less Pipeline ADCs. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Redundant SAR ADCs with Split-capacitor DAC. - Antonio Lopez-Angulo; Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (ICECS, 2018)

Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach. - Antonio J. Ginés; Antonio Lopez-Angulo; Eduardo J. Peralías; Adoración Rueda (ISCAS, 2018)

Mismatch and Offset Calibration in Redundant SAR ADC. - Antonio Lopez-Angulo; Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (DCIS, 2019)

Fast adaptive comparator offset calibration in pipeline ADC with self-repairing thermometer to binary encoder. - Antonio Jose Ginés; Eduardo José Peralías; Cristina Aledo; Adoración Rueda (Int. J. Circuit Theory Appl., 2019)

Calibration of Capacitor Mismatch and Static Comparator Offset in SAR ADC with Digital Redundancy. - Antonio Lopez-Angulo; Antonio J. Ginés; Eduardo J. Peralías (ISCAS, 2020)

Fast Simulation of Non-Linear Circuits using Semi-Analytical Solutions Based on the Matrix Exponential. - J. A. Serrano; Antonio J. Ginés; Eduardo J. Peralías (ISCAS, 2020)

Non-Linear Calibration of Pipeline ADCs using a Histogram-Based Estimation of the Redundant INL. - Antonio J. Ginés; Gildas Léger; Eduardo J. Peralías (NEWCAS, 2020)

Digital calibration of capacitor mismatch and comparison offset in Split-CDAC SAR ADCs with redundancy. - Antonio Lopez-Angulo; Antonio J. Ginés; Eduardo J. Peralías (NEWCAS, 2020)

Normalized Nonlinear Semiempirical MOST Model Used in Monolithic RF Class A-to-C PAs. - Rafaella Fiorelli; Nicolás Barabino; Fernando Silveira; Eduardo J. Peralías (Circuits Syst. Signal Process., 2020)

Digital Non-Linearity Calibration for ADCs With Redundancy Using a New LUT Approach. - Antonio J. Ginés; Gildas Léger; Eduardo J. Peralías (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A Single-Event Latchup setup for high-precision AMS circuits. - Gildas Léger; Antonio J. Ginés; Eduardo J. Peralías; Valentin Gutierrez; C. Dominguez; Maria Angeles Jalón; L. Carranza (ETS, 2023)

Behavioral Model for High-Speed SAR ADCs With On-Chip References. - Carlos Manuel Domínguez-Matas; Antonio J. Ginés; Aránzazu Otín; Valentin Gutierrez; Gildas Léger; Eduardo J. Peralías (IEEE Trans. Very Large Scale Integr. Syst., 2023)