Fault tolerant methods for reliability in FPGAs. - Edward A. Stott; N. Pete Sedcole; Peter Y. K. Cheung (FPL, 2008)

Compensating for variability in FPGAs by re-mapping and re-placement. - N. Pete Sedcole; Edward A. Stott; Peter Y. K. Cheung (FPL, 2009)

Degradation in FPGAs: measurement and modelling. - Edward A. Stott; Justin S. J. Wong; N. Pete Sedcole; Peter Y. K. Cheung (FPGA, 2010)

Degradation Analysis and Mitigation in FPGAs. - Edward A. Stott; Justin S. J. Wong; Peter Y. K. Cheung (FPL, 2010)

Fault tolerance and reliability in field-programmable gate arrays. - Edward A. Stott; N. Pete Sedcole; Peter Y. K. Cheung (IET Comput. Digit. Tech., 2010)

Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only). - Joshua M. Levine; Edward A. Stott; George A. Constantinides; Peter Y. K. Cheung (FPGA, 2011)

Improving FPGA Reliability with Wear-Levelling. - Edward A. Stott; Peter Y. K. Cheung (FPL, 2011)

Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling. - Joshua M. Levine; Edward A. Stott; George A. Constantinides; Peter Y. K. Cheung (FCCM, 2012)

SMI: Slack Measurement Insertion for online timing monitoring in FPGAs. - Joshua M. Levine; Edward A. Stott; George A. Constantinides; Peter Y. K. Cheung (FPL, 2013)

Variation and Reliability in FPGAs. - Edward A. Stott; Zhenyu Guan; Joshua M. Levine; Justin S. J. Wong; Peter Y. K. Cheung (IEEE Des. Test, 2013)

Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs. - Kan Shi; David Boland; Edward A. Stott; Samuel Bayliss; George A. Constantinides (DAC, 2014)

Timing Fault Detection in FPGA-Based Circuits. - Edward A. Stott; Joshua M. Levine; Peter Y. K. Cheung; Nachiket Kapre (FCCM, 2014)

Dynamic voltage & frequency scaling with online slack measurement. - Joshua M. Levine; Edward A. Stott; Peter Y. K. Cheung (FPGA, 2014)

Delay-Bounded Routing for Shadow Registers. - Eddie Hung; Joshua M. Levine; Edward A. Stott; George A. Constantinides; Wayne Luk (FPGA, 2015)

Adaptive energy minimization of embedded heterogeneous systems using regression-based learning. - Sheng Yang 003; Rishad A. Shafik; Geoff V. Merrett; Edward A. Stott; Joshua M. Levine; James J. Davis 001; Bashir M. Al-Hashimi (PATMOS, 2015)

KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. - Eddie Hung; James J. Davis 001; Joshua M. Levine; Edward A. Stott; Peter Y. K. Cheung; George A. Constantinides (FCCM, 2016)

Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). - James J. Davis 001; Eddie Hung; Joshua M. Levine; Edward A. Stott; Peter Y. K. Cheung; George A. Constantinides (FPGA, 2016)

STRIPE: Signal selection for runtime power estimation. - James J. Davis 001; Joshua M. Levine; Edward A. Stott; Eddie Hung; Peter Y. K. Cheung; George A. Constantinides (FPL, 2017)

KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications. - James J. Davis 001; Joshua M. Levine; Edward A. Stott; Eddie Hung; Peter Y. K. Cheung; George A. Constantinides (IEEE Des. Test, 2017)

KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications. - James J. Davis 001; Joshua M. Levine; Edward A. Stott; Eddie Hung; Peter Y. K. Cheung; George A. Constantinides (IWOCL, 2018)

KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. - James J. Davis 001; Eddie Hung; Joshua M. Levine; Edward A. Stott; Peter Y. K. Cheung; George A. Constantinides (ACM Trans. Reconfigurable Technol. Syst., 2018)