Sequential circuit synthesis using input delays - Edward B. Eichelberger (SWCT, 1963)

Hazard Detection in Combinational and Sequential Switching Circuits. - Edward B. Eichelberger (IBM J. Res. Dev., 1965)

A logic design structure for LSI testability. - Edward B. Eichelberger; Thomas W. Williams (DAC, 1977)

The Oregon Report Basic Technology. - Hollis L. Caswell; William C. Holton; Richard J. Petschauer; George A. Brown; S. Krishnaswamy; Herbert Stopper; Daniel H. Carter; William Lattin; Robert M. Sullivan; Edward B. Eichelberger; Paul Losleben (Computer, 1978)

A Heuristic Test-Pattern Generator for Programmable Logic Arrays. - Edward B. Eichelberger; Eric Lindbloom (IBM J. Res. Dev., 1980)

An LSSD Pseudo Random Pattern Test System. - Franco Motika; John A. Waicukauski; Edward B. Eichelberger; Eric Lindbloom (ITC, 1983)

Random-Pattern Coverage Enhancement and Diagnosis for LSSD Logic Self-Test. - Edward B. Eichelberger; Eric Lindbloom (IBM J. Res. Dev., 1983)

Experiences and Expectations in VLSI Testing. - Edward B. Eichelberger (ITC, 1985)

A Statistical Calculation of Fault Detection Probabilities By Fast Fault Simulation. - John A. Waicukauski; Eric Lindbloom; Edward B. Eichelberger; Donato O. Forlenza; Tim McCarthy (ITC, 1985)

A Method for Generating Weighted Random Test Patterns. - John A. Waicukauski; Eric Lindbloom; Edward B. Eichelberger; Orazio P. Forlenza (IBM J. Res. Dev., 1989)

IBM ES/9000 model 320 air cooled computer technology. - Venkappa L. Gani; Matthew Graf; Keith Mathews; Edward B. Eichelberger (Compcon, 1991)

Differential current switch-High performance at low power. - Edward B. Eichelberger; Stephen E. Bello (IBM J. Res. Dev., 1991)