A 133.6TOPS/W Compute-In-Memory SRAM Macro with Fully Parallel One-Step Multi-Bit Computation. - Edward Jongyoon Choi; Injun Choi; Chanhee Jeon; Gichan Yun; Donghyeon Yi; Sohmyung Ha; Ik-Joon Chang; Minkyu Je (CICC, 2022)

An SRAM-Based Hybrid Computation-in-Memory Macro Using Current-Reused Differential CCO. - Injun Choi; Edward Jongyoon Choi; Donghyeon Yi; Yoontae Jung; Hoyong Seong; Hyuntak Jeon; Soon-Jae Kweon; Ik-Joon Chang; Sohmyung Ha; Minkyu Je (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

A 333TOPS/W Logic-Compatible Multi-Level Embedded Flash Compute-In-Memory Macro with Dual-Slope Computation. - Edward Jongyoon Choi; Injun Choi; Vincent Lukito; Dong-Hwi Choi; Donghyeon Yi; Ik-Joon Chang; Sohmyung Ha; Minkyu Je (CICC, 2023)

A 639.38GOPS Hybrid-Domain Logic-Compatible Multi-Level Embedded Flash Computing-in-Memory Macro with Spike-Edge Computation. - Jiho Chun; Edward Jongyoon Choi; Byeongseon Choi; Donghyeon Yi; Sohmyung Ha; Ik-Joon Chang; Minkyu Je (A-SSCC, 2024)

An SRAM-based Error-Free Time Domain Pulse Train Computing-In-Memory Macro achieving 226.14 TOPS/W and 5.782 TOPS/mm2. - Edward Jongyoon Choi; Jiho Chun; Byeongseon Choi; Sohmyung Ha; Ik-Joon Chang; Minkyu Je (ISOCC, 2024)

A Δ-Based Spike Sorting SoC with End-to-End Implementation of Event-Driven Binary Autoencoder Neural Network in Analog CIM Achieving 94.54% Accuracy and 3.11μW/ch. - Edward Jongyoon Choi; Vincent Lukito; Injun Choi; Seoyoung Lee; Ik-Joon Chang; Sohmyung Ha; Minkyu Je (VLSI Technology and Circuits, 2024)

Skew-CIM: Process-Variation-Resilient and Energy-Efficient Computation-in-Memory Design Technique With Skewed Weights. - Donghyeon Yi; Seoyoung Lee; Injun Choi; Gichan Yun; Edward Jongyoon Choi; Jonghee Park; Jonghoon Kwak; Sung-Joon Jang; Sohmyung Ha; Ik-Joon Chang; Minkyu Je (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)