Comments on "An Algorithm for Synthesis of Multiple-Output Combinational Logic". - Edward S. Davidson; Gernot Metze (IEEE Trans. Computers, 1968)

An Algorithm for Nand Decomposition of Combinational Switching Functions - Edward S. Davidson (1968)

An Algorithm for NAND Decomposition Under Network Constraints. - Edward S. Davidson (IEEE Trans. Computers, 1969)

Authors' Reply4. - Edward S. Davidson; Gernot Metze (IEEE Trans. Computers, 1969)

A Transform for NAND Network Design. - Hsiao-Peng Lee; Edward S. Davidson (IEEE Trans. Computers, 1972)

Comments on "A Minimization Technique for TANT Networks". - Hsiao-Peng Lee; Edward S. Davidson (IEEE Trans. Computers, 1972)

Optimal Searching Algorithms for Parallel Pipelined Computers. - Daniel L. Weller; Edward S. Davidson (Sagamore Computer Conference, 1974)

A multiminiprocessor system implemented through pipelining. - Leonard E. Shar; Edward S. Davidson (Computer, 1974)

Redundancy Testing in Combinational Networks. - Hsien-Hsin S. Lee; Edward S. Davidson (IEEE Trans. Computers, 1974)

Improving the Throughput of a Pipeline by Insertion of Delays. - Janak H. Patel; Edward S. Davidson (ISCA, 1976)

Information Content of CPU Memory Referencing Behavior. - Dan W. Hammerstrom; Edward S. Davidson (ISCA, 1977)

Organization of Semiconductor Memories for Parallel-Pipelined Processors. - Faye A. Briggs; Edward S. Davidson (IEEE Trans. Computers, 1977)

Performance Evaluation of Highly Concurrent Computers by Deterministic Simulation. - B. Kumar; Edward S. Davidson (Commun. ACM, 1978)

Special Feature: Developing a Multiple-Instruction-Stream Single-Chip Processor. - William Joseph Kaminsky Jr.; Edward S. Davidson (Computer, 1979)

A Multiple Stream Microprocessor Prototype System: AMP-1. - Edward S. Davidson (ISCA, 1980)

Computer System Design Using a Hierarchical Approach to Performance Evaluation. - B. Kumar; Edward S. Davidson (Commun. ACM, 1980)

A Comparison of Dynamic and Static Virtual Memory Allocation Algorithms. - Robert L. Budzinski; Edward S. Davidson (IEEE Trans. Software Eng., 1981)

DMIN: An Algorithm for Computing the Optimal Dynamic Allocation in a Virtual Memory Computer. - Robert L. Budzinski; Edward S. Davidson; Wataru Mayeda; Harold S. Stone (IEEE Trans. Software Eng., 1981)

Evaluating database management systems. - Edward S. Davidson (AFIPS National Computer Conference, 1982)

Memory Interference in Synchronous Multiprocessor Systems. - David W. L. Yen; Janak H. Patel; Edward S. Davidson (IEEE Trans. Computers, 1982)

Structured Memory Access Architecture. - Andrew R. Pleszkun; Edward S. Davidson (ICPP, 1983)

Performance of Shared Cache for Parallel-Pipelined Computer Systems - Phil C. C. Yeh; Janak H. Patel; Edward S. Davidson (ISCA, 1983)

Shared Cache for Multiple-Stream Computer Systems. - Phil C. C. Yeh; Janak H. Patel; Edward S. Davidson (IEEE Trans. Computers, 1983)

Design of Instruction Set Architectures for Support of High-Level Languages . - Pradip Bose; Edward S. Davidson (ISCA, 1984)

A custom-designed integrated circuit for the realization of residue number digital filters. - W. K. Jenkins; Edward S. Davidson; D. F. Paul (ICASSP, 1985)

TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology. - Peter Y.-T. Hsu; Joseph T. Rahmeh; Edward S. Davidson; Jacob A. Abraham (ISCA, 1985)

An Efficient LISP-Execution Architecture with a New Representation for List Structures. - Gurindar S. Sohi; Edward S. Davidson; Janak H. Patel (ISCA, 1985)

A Broader Range of Possible Answers to the Issues Raised by RISC. - Edward S. Davidson (COMPCON, 1986)

Features of the Structured Memory Access (SMA) Architecture. - Andrew R. Pleszkun; Gurindar S. Sohi; Bassam Z. Kahhaleh; Edward S. Davidson (COMPCON, 1986)

A Communication Model for Optimizing Hierarchical Multiprocessor Systems. - Santosh G. Abraham; Edward S. Davidson (ICPP, 1986)

Highly Concurrent Scalar Processing. - Peter Y.-T. Hsu; Edward S. Davidson (ISCA, 1986)

PSOLVE : A Concurrent Algorithm for Solving Sparse Systems of Linear Equations. - Timothy A. Davis 001; Edward S. Davidson (ICPP, 1987)

Characterization of Branch and Data Dependencies in Programs for Evaluating Pipeline Performance. - Philip G. Emma; Edward S. Davidson (IEEE Trans. Computers, 1987)

An evaluation of Cray X-MP performance on vectorizable Livermore FORTRAN kernels. - J. H. Tang; Edward S. Davidson (ICS, 1988)

Analysis of Memory Referencing Behavior For Design of Local Memories. - Geoffrey D. McNiven; Edward S. Davidson (ISCA, 1988)

Polycyclic Vector scheduling vs. Chaining on 1-Port Vector supercomputers. - J. H. Tang; Edward S. Davidson; J. Tong (SC, 1988)

Pairwise Reduction for the Direct, Parallel Solution of Sparse, Unsymmetric Sets of Linear Equations. - Timothy A. Davis 001; Edward S. Davidson (IEEE Trans. Computers, 1988)

Cyclic job shop scheduling using reservation tables. - Jarir K. Chaar; Edward S. Davidson (ICRA, 1990)

Vector Register Design for Polycyclic Vector Scheduling. - William H. Mangione-Smith; Santosh G. Abraham; Edward S. Davidson (ASPLOS, 1991)

Optimal Clocking of Circular Pipelines. - Karem A. Sakallah; Trevor N. Mudge; Timothy M. Burks; Edward S. Davidson (ICCD, 1991)

The Organization of the Cedar System. - Jeff Konicek; Tracy Tilton; Alexander V. Veidenbaum; Chuan-Qi Zhu; Edward S. Davidson; Ruppert A. Downing; Michael J. Haney; Manish Sharma; Pen-Chung Yew; P. Michael Farmwald; David J. Kuck; Daniel M. Lavery; et al. (ICPP (1), 1991)

An integrated approach to developing manufacturing control software. - Jarir K. Chaar; Richard A. Volz; Edward S. Davidson (ICRA, 1991)

A Performance Comparison of the IBM RS/6000 and the Astronautics ZS-1. - William H. Mangione-Smith; Santosh G. Abraham; Edward S. Davidson (Computer, 1991)

Using constraint geometry to determine maximum rate pipeline clocking. - Chuan-Hua Chang; Edward S. Davidson; Karem A. Sakallah (ICCAD, 1992)

Register requirements of pipelined processors. - William H. Mangione-Smith; Santosh G. Abraham; Edward S. Davidson (ICS, 1992)

Evaluating the Communication Performance of MPPs Using Synthetic Sparse Matrix Multiplication Workloads. - Eric L. Boyd; John-David Wellman; Santosh G. Abraham; Edward S. Davidson (International Conference on Supercomputing, 1993)

KSR 1 Multiprocessor: Analysis of Latency Hiding Techniques in a Sparse Solver. - Daniel Windheiser; Eric L. Boyd; Eric Hao; Santosh G. Abraham; Edward S. Davidson (IPPS, 1993)

Hierarchical Performance Modeling with MACS: A Case Study of the Convex C-240. - Eric L. Boyd; Edward S. Davidson (ISCA, 1993)

The Cedar System and an Initial Performance Study. - David J. Kuck; Edward S. Davidson; Duncan H. Lawrie; Ahmed H. Sameh; Chuan-Qi Zhu; Alexander V. Veidenbaum; Jeff Konicek; Pen-Chung Yew; Kyle A. Gallivan; William Jalby; Harry A. G. Wijshoff; Randall Bramley; et al. (ISCA, 1993)

Approaching a machine-application bound in delivered performance on scientific code. - William H. Mangione-Smith; Tien-Pao Shih; Santosh G. Abraham; Edward S. Davidson (Proc. IEEE, 1993)

Synchronization of pipelines. - Karem A. Sakallah; Trevor N. Mudge; Timothy M. Burks; Edward S. Davidson (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Grouping Array Layouts to Reduce Communication and Improve Locality of Parallel Programs. - Tien-Pao Shih; Edward S. Davidson (ICPADS, 1994)

A Hierarchical Approach to Modeling and Improving the Performance of Scientific Applications on the KSR1. - Eric L. Boyd; Waqar Azeem; Hsien-Hsin S. Lee; Tien-Pao Shih; Shih-Hao Hung; Edward S. Davidson (ICPP (3), 1994)

Communication in the KSR1 MPP: performance evaluation using synthetic workload experiments. - Eric L. Boyd; Edward S. Davidson (International Conference on Supercomputing, 1994)

Optimal local register allocation for a multiple-issue machine. - Waleed Meleis; Edward S. Davidson (International Conference on Supercomputing, 1994)

Minimum register requirements for a modulo schedule. - Alexandre E. Eichenberger; Edward S. Davidson; Santosh G. Abraham (MICRO, 1994)

The resource conflict methodology for early-stage design space exploration of superscalar RISC processors. - John-David Wellman; Edward S. Davidson (ICCD, 1995)

Optimum Modulo Schedules for Minimum Register Requirements. - Alexandre E. Eichenberger; Edward S. Davidson; Santosh G. Abraham (International Conference on Supercomputing, 1995)

Register allocation for predicated code. - Alexandre E. Eichenberger; Edward S. Davidson (MICRO, 1995)

Stage scheduling: a technique to reduce the register requirements of a modulo schedule. - Alexandre E. Eichenberger; Edward S. Davidson (MICRO, 1995)

Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability. - Chuan-Hua Chang; Edward S. Davidson; Karem A. Sakallah (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based Design. - Jude A. Rivers; Edward S. Davidson (ICPP, Vol. 1, 1996)

Profile Driven Weighted Decomposition. - Karen A. Tomko; Edward S. Davidson (International Conference on Supercomputing, 1996)

Modeling the Communication Performance of the IBM SP2. - Gheith A. Abandah; Edward S. Davidson (IPPS, 1996)

A Reduced Multipipeline Machine Description that Preserves Scheduling Constraints. - Alexandre E. Eichenberger; Edward S. Davidson (PLDI, 1996)

Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Scheduling. - Alexandre E. Eichenberger; Edward S. Davidson; Santosh G. Abraham (Int. J. Parallel Program., 1996)

Performance Issues in Integrating Temporality-Based Caching with Prefetching. - Jude A. Rivers; Edward S. Davidson (Perform. Evaluation, 1996)

On Effective Data Supply For Multi-Issue Processors. - Jude A. Rivers; Edward S. Tam; Edward S. Davidson (ICCD, 1997)

On High-Bandwidth Data Cache Design for Multi-Issue Processors. - Jude A. Rivers; Gary S. Tyson; Edward S. Davidson; Todd M. Austin (MICRO, 1997)

Efficient Formulation for Optimal Modulo Schedulers. - Alexandre E. Eichenberger; Edward S. Davidson (PLDI, 1997)

Origin 2000 Design Enhancements for Communication Intensive Applications. - Gheith A. Abandah; Edward S. Davidson (IEEE PACT, 1998)

Evaluating the performance of active cache management schemes. - Edward S. Tam; Jude A. Rivers; Vijayalakshmi Srinivasan; Gary S. Tyson; Edward S. Davidson (ICCD, 1998)

Utilizing Reuse Information in Data Cache Management. - Jude A. Rivers; Edward S. Tam; Gary S. Tyson; Edward S. Davidson; Matthew K. Farrens (International Conference on Supercomputing, 1998)

Configuration Independent Analysis for Characterizing Shared-Memory Applications. - Gheith A. Abandah; Edward S. Davidson (IPPS/SPDP, 1998)

Effects of Architectural and Technological Advances on the HP/Convex Exemplar's Memory and Communication Performance. - Gheith A. Abandah; Edward S. Davidson (ISCA, 1998)

The Cedar System and an Initial Performance Study. - David J. Kuck; Edward S. Davidson; Duncan H. Lawrie; Ahmed H. Sameh; Chuan-Qi Zhu (25 Years ISCA: Retrospectives and Reprints, 1998)

Retrospective: The Cedar System. - Alexander V. Veidenbaum; Pen-Chung Yew; David J. Kuck; Constantine D. Polychronopoulos; David A. Padua; Edward S. Davidson; Kyle A. Gallivan (25 Years ISCA: Retrospectives and Reprints, 1998)

mlcache: A Flexible Multi-Lateral Cache Simulator. - Edward S. Tam; Jude A. Rivers; Gary S. Tyson; Edward S. Davidson (MASCOTS, 1998)

Characterizing Distributed Shared Memory Performance: A Case Study of the Convex SPP1000. - Gheith A. Abandah; Edward S. Davidson (IEEE Trans. Parallel Distributed Syst., 1998)

Dual-Issue Scheduling with Spills for Binary Trees. - Waleed Meleis; Edward S. Davidson (SODA, 1999)

Introduction to "The ENIAC". - Arthur W. Burks; Edward S. Davidson (Proc. IEEE, 1999)

Active Management of Data Caches by Exploiting Reuse Information. - Edward S. Tam; Jude A. Rivers; Vijayalakshmi Srinivasan; Gary S. Tyson; Edward S. Davidson (IEEE Trans. Computers, 1999)

Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining. - Mikhail Smelyanskiy; Gary S. Tyson; Edward S. Davidson (IEEE PACT, 2000)

Instruction overhead and data locality effects in superscalar processors. - Murali Annavaram; Gary S. Tyson; Edward S. Davidson (ISPASS, 2000)

Improving BTB performance in the presence of DLLs. - Stevan A. Vlaovic; Edward S. Davidson; Gary S. Tyson (MICRO, 2000)

Branch History Guided Instruction Prefetching. - Viji Srinivasan; Edward S. Davidson; Gary S. Tyson; Mark J. Charney; Thomas R. Puzak (HPCA, 2001)

Allocation by Conflict: A Simple Effective Multilateral Cache Management Scheme. - Edward S. Tam; Stevan A. Vlaovic; Gary S. Tyson; Edward S. Davidson (ICCD, 2001)

Data prefetching by dependence graph precomputation. - Murali Annavaram; Jignesh M. Patel; Edward S. Davidson (ISCA, 2001)

Evaluating the Use of Register Queues in Software Pipelined Loops. - Gary S. Tyson; Mikhail Smelyanskiy; Edward S. Davidson (IEEE Trans. Computers, 2001)

TAXI: Trace Analysis for X86 Interpretation. - Stevan A. Vlaovic; Edward S. Davidson (ICCD, 2002)

Boosting trace cache performance with nonhead miss speculation. - Stevan A. Vlaovic; Edward S. Davidson (ICS, 2002)

Predicate-Aware Scheduling: A Technique for Reducing Resource Constraints. - Mikhail Smelyanskiy; Scott A. Mahlke; Edward S. Davidson; Hsien-Hsin S. Lee (CGO, 2003)

Call graph prefetching for database applications. - Murali Annavaram; Jignesh M. Patel; Edward S. Davidson (ACM Trans. Comput. Syst., 2003)

Probabilistic Predicate-Aware Modulo Scheduling. - Mikhail Smelyanskiy; Scott A. Mahlke; Edward S. Davidson (CGO, 2004)

A Prefetch Taxonomy. - Viji Srinivasan; Edward S. Davidson; Gary S. Tyson (IEEE Trans. Computers, 2004)

A freespace crossbar for multi-core processors. - Michel N. Victor; Aris K. Silzars; Edward S. Davidson (ICS, 2008)

Author retrospective for optimum modulo schedules for minimum register requirements. - Alexandre E. Eichenberger; Edward S. Davidson; Santosh G. Abraham (ICS 25th Anniversary, 2014)